fa.vhd

为了给大家紧张的工作减轻点负担

--bypass adder 子单元
library ieee;
use ieee.std_logic_1164.all;

entity Fa is 
	port (Pi,Gi,Ci:in std_logic;
		Coi,Si:out std_logic
		);
end Fa;
architecture Fabehav of Fa is
begin
	Coi<=Gi or (Pi and Ci);
	Si<=Pi xor Ci;
end Fabehav;