📄 bypass_adder.sim.rpt
字号:
; |bypass_adder|Sum[14] ; |bypass_adder|Sum[14] ; pin_out ;
; |bypass_adder|Sum[15] ; |bypass_adder|Sum[15] ; pin_out ;
; |bypass_adder|Sum[16] ; |bypass_adder|Sum[16] ; pin_out ;
; |bypass_adder|Sum[17] ; |bypass_adder|Sum[17] ; pin_out ;
; |bypass_adder|Sum[18] ; |bypass_adder|Sum[18] ; pin_out ;
; |bypass_adder|Sum[19] ; |bypass_adder|Sum[19] ; pin_out ;
; |bypass_adder|Sum[20] ; |bypass_adder|Sum[20] ; pin_out ;
; |bypass_adder|Sum[21] ; |bypass_adder|Sum[21] ; pin_out ;
; |bypass_adder|Sum[22] ; |bypass_adder|Sum[22] ; pin_out ;
; |bypass_adder|Sum[23] ; |bypass_adder|Sum[23] ; pin_out ;
; |bypass_adder|Sum[24] ; |bypass_adder|Sum[24] ; pin_out ;
; |bypass_adder|Sum[25] ; |bypass_adder|Sum[25] ; pin_out ;
; |bypass_adder|Sum[26] ; |bypass_adder|Sum[26] ; pin_out ;
; |bypass_adder|Sum[27] ; |bypass_adder|Sum[27] ; pin_out ;
; |bypass_adder|Co ; |bypass_adder|Co ; pin_out ;
; |bypass_adder|testp[0] ; |bypass_adder|testp[0] ; pin_out ;
; |bypass_adder|testp[1] ; |bypass_adder|testp[1] ; pin_out ;
; |bypass_adder|testp[2] ; |bypass_adder|testp[2] ; pin_out ;
; |bypass_adder|testp[3] ; |bypass_adder|testp[3] ; pin_out ;
; |bypass_adder|testp[4] ; |bypass_adder|testp[4] ; pin_out ;
; |bypass_adder|testp[5] ; |bypass_adder|testp[5] ; pin_out ;
; |bypass_adder|testp[6] ; |bypass_adder|testp[6] ; pin_out ;
; |bypass_adder|testp[7] ; |bypass_adder|testp[7] ; pin_out ;
; |bypass_adder|testp[8] ; |bypass_adder|testp[8] ; pin_out ;
; |bypass_adder|testp[9] ; |bypass_adder|testp[9] ; pin_out ;
; |bypass_adder|testp[10] ; |bypass_adder|testp[10] ; pin_out ;
; |bypass_adder|testp[11] ; |bypass_adder|testp[11] ; pin_out ;
; |bypass_adder|testp[12] ; |bypass_adder|testp[12] ; pin_out ;
; |bypass_adder|testp[13] ; |bypass_adder|testp[13] ; pin_out ;
; |bypass_adder|testp[14] ; |bypass_adder|testp[14] ; pin_out ;
; |bypass_adder|testp[15] ; |bypass_adder|testp[15] ; pin_out ;
; |bypass_adder|testp[16] ; |bypass_adder|testp[16] ; pin_out ;
; |bypass_adder|testp[17] ; |bypass_adder|testp[17] ; pin_out ;
; |bypass_adder|testp[18] ; |bypass_adder|testp[18] ; pin_out ;
; |bypass_adder|testp[19] ; |bypass_adder|testp[19] ; pin_out ;
; |bypass_adder|testp[20] ; |bypass_adder|testp[20] ; pin_out ;
; |bypass_adder|testp[21] ; |bypass_adder|testp[21] ; pin_out ;
; |bypass_adder|testp[22] ; |bypass_adder|testp[22] ; pin_out ;
; |bypass_adder|testp[23] ; |bypass_adder|testp[23] ; pin_out ;
; |bypass_adder|testp[24] ; |bypass_adder|testp[24] ; pin_out ;
; |bypass_adder|testp[25] ; |bypass_adder|testp[25] ; pin_out ;
; |bypass_adder|testp[26] ; |bypass_adder|testp[26] ; pin_out ;
; |bypass_adder|testp[27] ; |bypass_adder|testp[27] ; pin_out ;
; |bypass_adder|Fa:\G2:27:l2|Si ; |bypass_adder|Fa:\G2:27:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:26:l2|Coi~0 ; |bypass_adder|Fa:\G2:26:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:26:l2|Coi ; |bypass_adder|Fa:\G2:26:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:26:l2|Si ; |bypass_adder|Fa:\G2:26:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:25:l2|Coi~0 ; |bypass_adder|Fa:\G2:25:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:25:l2|Coi ; |bypass_adder|Fa:\G2:25:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:25:l2|Si ; |bypass_adder|Fa:\G2:25:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:24:l2|Coi~0 ; |bypass_adder|Fa:\G2:24:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:24:l2|Coi ; |bypass_adder|Fa:\G2:24:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:24:l2|Si ; |bypass_adder|Fa:\G2:24:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:23:l2|Coi~0 ; |bypass_adder|Fa:\G2:23:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:23:l2|Coi ; |bypass_adder|Fa:\G2:23:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:23:l2|Si ; |bypass_adder|Fa:\G2:23:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:22:l2|Coi~0 ; |bypass_adder|Fa:\G2:22:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:22:l2|Coi ; |bypass_adder|Fa:\G2:22:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:22:l2|Si ; |bypass_adder|Fa:\G2:22:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:21:l2|Coi~0 ; |bypass_adder|Fa:\G2:21:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:21:l2|Coi ; |bypass_adder|Fa:\G2:21:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:21:l2|Si ; |bypass_adder|Fa:\G2:21:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:20:l2|Coi~0 ; |bypass_adder|Fa:\G2:20:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:20:l2|Coi ; |bypass_adder|Fa:\G2:20:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:20:l2|Si ; |bypass_adder|Fa:\G2:20:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:19:l2|Coi~0 ; |bypass_adder|Fa:\G2:19:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:19:l2|Coi ; |bypass_adder|Fa:\G2:19:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:19:l2|Si ; |bypass_adder|Fa:\G2:19:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:18:l2|Coi~0 ; |bypass_adder|Fa:\G2:18:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:18:l2|Coi ; |bypass_adder|Fa:\G2:18:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:18:l2|Si ; |bypass_adder|Fa:\G2:18:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:17:l2|Coi~0 ; |bypass_adder|Fa:\G2:17:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:17:l2|Coi ; |bypass_adder|Fa:\G2:17:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:17:l2|Si ; |bypass_adder|Fa:\G2:17:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:16:l2|Coi~0 ; |bypass_adder|Fa:\G2:16:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:16:l2|Coi ; |bypass_adder|Fa:\G2:16:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:16:l2|Si ; |bypass_adder|Fa:\G2:16:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:15:l2|Coi~0 ; |bypass_adder|Fa:\G2:15:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:15:l2|Coi ; |bypass_adder|Fa:\G2:15:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:15:l2|Si ; |bypass_adder|Fa:\G2:15:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:14:l2|Coi~0 ; |bypass_adder|Fa:\G2:14:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:14:l2|Coi ; |bypass_adder|Fa:\G2:14:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:14:l2|Si ; |bypass_adder|Fa:\G2:14:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:13:l2|Coi~0 ; |bypass_adder|Fa:\G2:13:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:13:l2|Coi ; |bypass_adder|Fa:\G2:13:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:13:l2|Si ; |bypass_adder|Fa:\G2:13:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:12:l2|Coi~0 ; |bypass_adder|Fa:\G2:12:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:12:l2|Coi ; |bypass_adder|Fa:\G2:12:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:12:l2|Si ; |bypass_adder|Fa:\G2:12:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:11:l2|Coi~0 ; |bypass_adder|Fa:\G2:11:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:11:l2|Coi ; |bypass_adder|Fa:\G2:11:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:11:l2|Si ; |bypass_adder|Fa:\G2:11:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:10:l2|Coi~0 ; |bypass_adder|Fa:\G2:10:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:10:l2|Coi ; |bypass_adder|Fa:\G2:10:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:10:l2|Si ; |bypass_adder|Fa:\G2:10:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:9:l2|Coi~0 ; |bypass_adder|Fa:\G2:9:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:9:l2|Coi ; |bypass_adder|Fa:\G2:9:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:9:l2|Si ; |bypass_adder|Fa:\G2:9:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:8:l2|Coi~0 ; |bypass_adder|Fa:\G2:8:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:8:l2|Coi ; |bypass_adder|Fa:\G2:8:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:8:l2|Si ; |bypass_adder|Fa:\G2:8:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:7:l2|Coi~0 ; |bypass_adder|Fa:\G2:7:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:7:l2|Coi ; |bypass_adder|Fa:\G2:7:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:7:l2|Si ; |bypass_adder|Fa:\G2:7:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:6:l2|Coi~0 ; |bypass_adder|Fa:\G2:6:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:6:l2|Coi ; |bypass_adder|Fa:\G2:6:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:6:l2|Si ; |bypass_adder|Fa:\G2:6:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:5:l2|Coi~0 ; |bypass_adder|Fa:\G2:5:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:5:l2|Coi ; |bypass_adder|Fa:\G2:5:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:5:l2|Si ; |bypass_adder|Fa:\G2:5:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:4:l2|Coi~0 ; |bypass_adder|Fa:\G2:4:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:4:l2|Coi ; |bypass_adder|Fa:\G2:4:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:4:l2|Si ; |bypass_adder|Fa:\G2:4:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:3:l2|Coi~0 ; |bypass_adder|Fa:\G2:3:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:3:l2|Coi ; |bypass_adder|Fa:\G2:3:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:3:l2|Si ; |bypass_adder|Fa:\G2:3:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:2:l2|Coi~0 ; |bypass_adder|Fa:\G2:2:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:2:l2|Coi ; |bypass_adder|Fa:\G2:2:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:2:l2|Si ; |bypass_adder|Fa:\G2:2:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:1:l2|Coi~0 ; |bypass_adder|Fa:\G2:1:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:1:l2|Coi ; |bypass_adder|Fa:\G2:1:l2|Coi ; out0 ;
; |bypass_adder|Fa:\G2:1:l2|Si ; |bypass_adder|Fa:\G2:1:l2|Si ; out0 ;
; |bypass_adder|Fa:\G2:0:l2|Coi~0 ; |bypass_adder|Fa:\G2:0:l2|Coi~0 ; out0 ;
; |bypass_adder|Fa:\G2:0:l2|Coi ; |bypass_adder|Fa:\G2:0:l2|Coi ; out0 ;
; |bypass_adder|PGNet:\G1:27:l1|Pi ; |bypass_adder|PGNet:\G1:27:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:26:l1|Pi ; |bypass_adder|PGNet:\G1:26:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:25:l1|Pi ; |bypass_adder|PGNet:\G1:25:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:24:l1|Pi ; |bypass_adder|PGNet:\G1:24:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:23:l1|Pi ; |bypass_adder|PGNet:\G1:23:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:22:l1|Pi ; |bypass_adder|PGNet:\G1:22:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:21:l1|Pi ; |bypass_adder|PGNet:\G1:21:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:20:l1|Pi ; |bypass_adder|PGNet:\G1:20:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:19:l1|Pi ; |bypass_adder|PGNet:\G1:19:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:18:l1|Pi ; |bypass_adder|PGNet:\G1:18:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:17:l1|Pi ; |bypass_adder|PGNet:\G1:17:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:16:l1|Pi ; |bypass_adder|PGNet:\G1:16:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:15:l1|Pi ; |bypass_adder|PGNet:\G1:15:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:14:l1|Pi ; |bypass_adder|PGNet:\G1:14:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:13:l1|Pi ; |bypass_adder|PGNet:\G1:13:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:12:l1|Pi ; |bypass_adder|PGNet:\G1:12:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:11:l1|Pi ; |bypass_adder|PGNet:\G1:11:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:10:l1|Pi ; |bypass_adder|PGNet:\G1:10:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:9:l1|Pi ; |bypass_adder|PGNet:\G1:9:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:8:l1|Pi ; |bypass_adder|PGNet:\G1:8:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:7:l1|Pi ; |bypass_adder|PGNet:\G1:7:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:6:l1|Pi ; |bypass_adder|PGNet:\G1:6:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:5:l1|Pi ; |bypass_adder|PGNet:\G1:5:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:4:l1|Pi ; |bypass_adder|PGNet:\G1:4:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:3:l1|Pi ; |bypass_adder|PGNet:\G1:3:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:2:l1|Pi ; |bypass_adder|PGNet:\G1:2:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:2:l1|Gi ; |bypass_adder|PGNet:\G1:2:l1|Gi ; out0 ;
; |bypass_adder|PGNet:\G1:1:l1|Pi ; |bypass_adder|PGNet:\G1:1:l1|Pi ; out0 ;
; |bypass_adder|PGNet:\G1:1:l1|Gi ; |bypass_adder|PGNet:\G1:1:l1|Gi ; out0 ;
; |bypass_adder|PGNet:\G1:0:l1|Pi ; |bypass_adder|PGNet:\G1:0:l1|Pi ; out0 ;
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