bypass_adder.vhd

为了给大家紧张的工作减轻点负担

--传播进位加法器
library ieee;
use ieee.std_logic_1164.all;

entity bypass_adder is
	port(A,B:in std_logic_vector(27 downto 0);
		Ci:in std_logic;
		Sum:out std_logic_vector(27 downto 0);
		Co:out std_logic;
		testp:out std_logic_vector(27 downto 0)
		);
end bypass_adder;
architecture adderbehav of bypass_adder is
component Fa is
	port (Pi,Gi,Ci:in std_logic;
		Coi,Si:out std_logic
		);
end component;
component PGNet is
	port(Ai,Bi:in std_logic;
		Pi,Gi:out std_logic
		);
end component;

signal P,G:std_logic_vector(27 downto 0);
signal C:std_logic_vector(28 downto 0);
signal BP:std_logic;
begin
	C(0)<=Ci;
	G1: for i in 0 to 27 generate
	l1: PGNet port map(A(i),B(i),P(i),G(i));
	end generate G1;
	
	G2: for i in 0 to 27 generate
	l2:Fa port map (P(i),G(i),C(i),C(i+1),Sum(i));
	end generate G2;
	testp<=P;
	BP<='1' when P="11111111111111111111111111111111" else
		'0';
	Co<=Ci when BP='1' else
		C(8);

end adderbehav;