squre_root_unit.vhd

为了给大家紧张的工作减轻点负担

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity square_root_unit is
	generic (n:natural:=4);
	port (A: in std_logic_vector(n-1 downto 0);
		  B: in std_logic_vector(n-1 downto 0);
		 sum0,sum1:out std_logic_vector(n-1 downto 0);
		 co0,co1:out std_logic
		);
end square_root_unit;

architecture behav of square_root_unit is
signal ct0,ct1:std_logic_vector(n downto 0);
component fulladd is
	port (A: in std_logic;
		  B: in std_logic;
		 cin:in std_logic;
		 sumbit:out std_logic;
		cout:out std_logic
		);
end component;
begin
ct0(0)<='0';
ct1(0)<='1';
G1: for i in 0 to n-1 generate
	l1:fulladd port map (A(i),B(i),ct0(i),sum0(i),ct0(i+1));
	l2:fulladd port map (A(i),B(i),ct1(i),sum1(i),ct1(i+1));
end generate G1;
co0<=ct0(n);
co1<=ct1(n);
end behav;