square_root_adder.vhd

为了给大家紧张的工作减轻点负担

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity square_root_adder is
	port (A: in std_logic_vector(27 downto 0);
		  B: in std_logic_vector(27 downto 0);
		 ci: in std_logic;
		 sum:out std_logic_vector(27 downto 0);
		 co:out std_logic
		);
end square_root_adder;

architecture behav of square_root_adder is
signal c:std_logic_vector(4 downto 0);
signal sum0,sum1:std_logic_vector(27 downto 0);
signal co0,co1:std_logic_vector(3 downto 0);
signal m,n:natural;
component square_root_unit is
	generic (n:natural);
	port (A: in std_logic_vector(n-1 downto 0);
		  B: in std_logic_vector(n-1 downto 0);
		 sum0,sum1:out std_logic_vector(n-1 downto 0);
		 co0,co1:out std_logic
		);
end component;

begin

G1: for i in 0 to 3 generate
	c(i+1)<=co0(i) when c(i)='0' else
			co1(i);
end generate G1;

l0:square_root_unit generic map (2) port map (A(1 downto 0),B(1 downto 0),sum0(1 downto 0),sum1(1 downto 0),co0(0),co1(0));
sum(1 downto 0)<=sum0(1 downto 0) when c(0)='0' else sum1(1 downto 0);
l1:square_root_unit generic map (4) port map (A(5 downto 2),B(5 downto 2),sum0(5 downto 2),sum1(5 downto 2),co0(1),co1(1));
sum(5 downto 2)<=sum0(5 downto 2) when c(1)='0' else sum1(5 downto 2);
l2:square_root_unit generic map (8) port map (A(13 downto 6),B(13 downto 6),sum0(13 downto 6),sum1(13 downto 6),co0(2),co1(2));
sum(13 downto 6)<=sum0(13 downto 6) when c(2)='0' else sum1(13 downto 6);
l3:square_root_unit generic map (14) port map (A(27 downto 14),B(27 downto 14),sum0(27 downto 14),sum1(27 downto 14),co0(3),co1(3));
sum(27 downto 14)<=sum0(27 downto 14) when c(3)='0' else sum1(27 downto 14);

c(0)<=ci;
co<=c(4);

end behav;