square_root_unit_test.vhd

为了给大家紧张的工作减轻点负担

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity square_root_unit_test is
	port (A: in std_logic_vector(5 downto 0);
		  B: in std_logic_vector(5 downto 0);
		 ci: in std_logic;
		 sum:out std_logic_vector(5 downto 0);
		 co:out std_logic
		);
end square_root_unit_test;

architecture behav of square_root_unit_test is
signal sum0,sum1:std_logic_vector(5 downto 0);
signal m:natural:=5;
signal co0,co1:std_logic;
component square_root_unit is
	generic (n:natural:=6);
	port (A: in std_logic_vector(n-1 downto 0);
		  B: in std_logic_vector(n-1 downto 0);
		 sum0,sum1:out std_logic_vector(n-1 downto 0);
		 co0,co1:out std_logic
		);
end component;

begin
u1:square_root_unit generic map (6) port map(A,B,sum0,sum1,co0,co1);
	co<=co0 when ci='0' else
		co1;
	sum<=sum0 when ci='0' else
		 sum1;

end behav;