liner_adder.hif

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Version 6.0 Build 178 04/27/2006 SJ Full Version
39
2097
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
fulladd
# storage
db|liner_adder.(2).cnf
db|liner_adder.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fulladd.vhd
aeea8271d04381d2196b6c21128d15e1
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
liner_adder_unit:\G1:0:l1|fulladd:\G1:0:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:0:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:1:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:1:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:2:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:2:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:3:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:3:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:4:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:4:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:5:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:5:l2
liner_adder_unit:\G1:0:l1|fulladd:\G1:6:l1
liner_adder_unit:\G1:0:l1|fulladd:\G1:6:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:0:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:0:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:1:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:1:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:2:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:2:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:3:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:3:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:4:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:4:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:5:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:5:l2
liner_adder_unit:\G1:1:l1|fulladd:\G1:6:l1
liner_adder_unit:\G1:1:l1|fulladd:\G1:6:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:0:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:0:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:1:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:1:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:2:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:2:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:3:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:3:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:4:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:4:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:5:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:5:l2
liner_adder_unit:\G1:2:l1|fulladd:\G1:6:l1
liner_adder_unit:\G1:2:l1|fulladd:\G1:6:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:0:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:0:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:1:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:1:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:2:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:2:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:3:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:3:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:4:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:4:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:5:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:5:l2
liner_adder_unit:\G1:3:l1|fulladd:\G1:6:l1
liner_adder_unit:\G1:3:l1|fulladd:\G1:6:l2
}
# end
# entity
liner_adder
# storage
db|liner_adder.(0).cnf
db|liner_adder.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
liner_adder.vhd
5755a8b37413c7afc92b2ed4e8f058ff
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
liner_adder_unit.vhd
f52bf81be8189fb690278b3bbf2b5a
fulladd.vhd
aeea8271d04381d2196b6c21128d15e1
liner_adder.vhd
5755a8b37413c7afc92b2ed4e8f058ff
}
# hierarchies {
|
}
# end
# entity
liner_adder_unit
# storage
db|liner_adder.(1).cnf
db|liner_adder.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
liner_adder_unit.vhd
f52bf81be8189fb690278b3bbf2b5a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(a)
6 downto 0
PARAMETER_STRING
USR
 constraint(b)
6 downto 0
PARAMETER_STRING
USR
 constraint(sum0)
6 downto 0
PARAMETER_STRING
USR
}
# include_file {
liner_adder_unit.vhd
f52bf81be8189fb690278b3bbf2b5a
fulladd.vhd
aeea8271d04381d2196b6c21128d15e1
liner_adder.vhd
5755a8b37413c7afc92b2ed4e8f058ff
}
# hierarchies {
liner_adder_unit:\G1:0:l1
liner_adder_unit:\G1:1:l1
liner_adder_unit:\G1:2:l1
liner_adder_unit:\G1:3:l1
}
# end
# complete