liner_adder.tan.rpt

为了给大家紧张的工作减轻点负担

Timing Analyzer report for liner_adder
Fri Dec 14 00:24:21 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 24.116 ns   ; A[1] ; co ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+---------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From  ; To      ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+---------+
; N/A                                     ; None                                                ; 24.116 ns       ; A[1]  ; co      ;
; N/A                                     ; None                                                ; 24.103 ns       ; B[1]  ; co      ;
; N/A                                     ; None                                                ; 23.931 ns       ; A[0]  ; co      ;
; N/A                                     ; None                                                ; 23.923 ns       ; B[0]  ; co      ;
; N/A                                     ; None                                                ; 23.289 ns       ; A[1]  ; sum[27] ;
; N/A                                     ; None                                                ; 23.276 ns       ; B[1]  ; sum[27] ;
; N/A                                     ; None                                                ; 23.249 ns       ; ci    ; co      ;
; N/A                                     ; None                                                ; 23.104 ns       ; A[0]  ; sum[27] ;
; N/A                                     ; None                                                ; 23.096 ns       ; B[0]  ; sum[27] ;
; N/A                                     ; None                                                ; 23.042 ns       ; A[3]  ; co      ;
; N/A                                     ; None                                                ; 22.905 ns       ; B[3]  ; co      ;
; N/A                                     ; None                                                ; 22.784 ns       ; A[4]  ; co      ;
; N/A                                     ; None                                                ; 22.747 ns       ; A[1]  ; sum[24] ;
; N/A                                     ; None                                                ; 22.734 ns       ; B[1]  ; sum[24] ;
; N/A                                     ; None                                                ; 22.732 ns       ; B[4]  ; co      ;
; N/A                                     ; None                                                ; 22.571 ns       ; A[2]  ; co      ;
; N/A                                     ; None                                                ; 22.562 ns       ; A[0]  ; sum[24] ;
; N/A                                     ; None                                                ; 22.554 ns       ; B[0]  ; sum[24] ;
; N/A                                     ; None                                                ; 22.461 ns       ; B[2]  ; co      ;
; N/A                                     ; None                                                ; 22.422 ns       ; ci    ; sum[27] ;
; N/A                                     ; None                                                ; 22.358 ns       ; A[1]  ; sum[23] ;
; N/A                                     ; None                                                ; 22.345 ns       ; B[1]  ; sum[23] ;
; N/A                                     ; None                                                ; 22.307 ns       ; A[1]  ; sum[25] ;
; N/A                                     ; None                                                ; 22.302 ns       ; A[1]  ; sum[26] ;
; N/A                                     ; None                                                ; 22.294 ns       ; B[1]  ; sum[25] ;
; N/A                                     ; None                                                ; 22.289 ns       ; B[1]  ; sum[26] ;
; N/A                                     ; None                                                ; 22.215 ns       ; A[3]  ; sum[27] ;
; N/A                                     ; None                                                ; 22.173 ns       ; A[0]  ; sum[23] ;
; N/A                                     ; None                                                ; 22.165 ns       ; B[0]  ; sum[23] ;
; N/A                                     ; None                                                ; 22.122 ns       ; A[0]  ; sum[25] ;