liner_adder.vhd

为了给大家紧张的工作减轻点负担

-- 线性进位加法器
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity liner_adder is
	port (A: in std_logic_vector(27 downto 0);
		  B: in std_logic_vector(27 downto 0);
		 ci: in std_logic;
		 sum:out std_logic_vector(27 downto 0);
		 co:out std_logic
		);
end liner_adder;

architecture behav of liner_adder is
signal c:std_logic_vector(4 downto 0);
signal sum0,sum1:std_logic_vector(27 downto 0);
signal co0,co1:std_logic_vector(3 downto 0);
component liner_adder_unit is
	port (A: in std_logic_vector(6 downto 0);
		  B: in std_logic_vector(6 downto 0);
		 sum0,sum1:out std_logic_vector(6 downto 0);
		 co0,co1:out std_logic
		);
end component;
begin

G1: for i in 0 to 3 generate
	l1:liner_adder_unit port map (A(i*7+6 downto i*7),B(i*7+6 downto i*7),
		sum0(i*7+6 downto i*7),sum1(i*7+6 downto i*7),co0(i),co1(i));
		c(i+1)<=co0(i) when c(i)='0' else
				co1(i);
		sum(i*7+6 downto i*7)<=sum0(i*7+6 downto i*7) when c(i)='0' else
								sum1(i*7+6 downto i*7);
end generate G1;
c(0)<=ci;
co<=c(4);
end behav;