carry_propogate_adder.fit.summary

来自「为了给大家紧张的工作减轻点负担」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Thu Dec 13 01:07:49 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : carry_propogate_adder
Top-level Entity Name : carry_propogate_adder
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 56 / 10,570 ( < 1 % )
Total pins : 86 / 336 ( 26 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )