carry_propogate_adder.vhd

为了给大家紧张的工作减轻点负担

--传播进位加法器
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity carry_propogate_adder is
	port (A: in std_logic_vector(27 downto 0);
		  B: in std_logic_vector(27 downto 0);
		 cin:in std_logic;
		 sum:out std_logic_vector(27 downto 0);
		cout:out std_logic
		);
end carry_propogate_adder;

architecture behav of carry_propogate_adder is
signal ct:std_logic_vector(28 downto 0);
component fulladd is
	port (A: in std_logic;
		  B: in std_logic;
		 cin:in std_logic;
		 sumbit:out std_logic;
		cout:out std_logic
		);
end component;
begin
ct(0)<=cin;
cout<=ct(28);
G1: for i in 0 to 27 generate
	l1:fulladd port map (A(i),B(i),ct(i),sum(i),ct(i+1));
end generate G1;
end behav;