prev_cmp_seg7led.tan.qmsg

FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk~0 register irrecv:inst2\|TimerCnt\[0\] register irrecv:inst2\|RecvState.STARTDOWN 14.675 ns " "Info: Slack time is 14.675 ns for clock \"clk~0\" between source register \"irrecv:inst2\|TimerCnt\[0\]\" and destination register \"irrecv:inst2\|RecvState.STARTDOWN\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "187.79 MHz 5.325 ns " "Info: Fmax is 187.79 MHz (period= 5.325 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.736 ns + Largest register register " "Info: + Largest register to register requirement is 19.736 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 17.797 ns " "Info: + Latch edge is 17.797 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Destination clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.203 ns " "Info: - Launch edge is -2.203 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Source clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 destination 5.946 ns + Shortest register " "Info: + Shortest clock path from clock \"clk~0\" to destination register is 5.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.666 ns) 5.946 ns irrecv:inst2\|RecvState.STARTDOWN 5 REG LCFF_X20_Y6_N31 2 " "Info: 5: + IC(0.824 ns) + CELL(0.666 ns) = 5.946 ns; Loc. = LCFF_X20_Y6_N31; Fanout = 2; REG Node = 'irrecv:inst2\|RecvState.STARTDOWN'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.51 % ) " "Info: Total cell delay = 1.636 ns ( 27.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns ( 72.49 % ) " "Info: Total interconnect delay = 4.310 ns ( 72.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 source 5.946 ns - Longest register " "Info: - Longest clock path from clock \"clk~0\" to source register is 5.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.666 ns) 5.946 ns irrecv:inst2\|TimerCnt\[0\] 5 REG LCFF_X20_Y6_N21 4 " "Info: 5: + IC(0.824 ns) + CELL(0.666 ns) = 5.946 ns; Loc. = LCFF_X20_Y6_N21; Fanout = 4; REG Node = 'irrecv:inst2\|TimerCnt\[0\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.51 % ) " "Info: Total cell delay = 1.636 ns ( 27.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns ( 72.49 % ) " "Info: Total interconnect delay = 4.310 ns ( 72.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.061 ns - Longest register register " "Info: - Longest register to register delay is 5.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns irrecv:inst2\|TimerCnt\[0\] 1 REG LCFF_X20_Y6_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y6_N21; Fanout = 4; REG Node = 'irrecv:inst2\|TimerCnt\[0\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.651 ns) 1.136 ns irrecv:inst2\|RecvState~311 2 COMB LCCOMB_X20_Y6_N14 2 " "Info: 2: + IC(0.485 ns) + CELL(0.651 ns) = 1.136 ns; Loc. = LCCOMB_X20_Y6_N14; Fanout = 2; COMB Node = 'irrecv:inst2\|RecvState~311'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.136 ns" { irrecv:inst2|TimerCnt[0] irrecv:inst2|RecvState~311 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.624 ns) 2.151 ns irrecv:inst2\|always1~174 3 COMB LCCOMB_X20_Y6_N24 1 " "Info: 3: + IC(0.391 ns) + CELL(0.624 ns) = 2.151 ns; Loc. = LCCOMB_X20_Y6_N24; Fanout = 1; COMB Node = 'irrecv:inst2\|always1~174'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.015 ns" { irrecv:inst2|RecvState~311 irrecv:inst2|always1~174 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.319 ns) 2.851 ns irrecv:inst2\|always1~175 4 COMB LCCOMB_X20_Y6_N12 2 " "Info: 4: + IC(0.381 ns) + CELL(0.319 ns) = 2.851 ns; Loc. = LCCOMB_X20_Y6_N12; Fanout = 2; COMB Node = 'irrecv:inst2\|always1~175'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.700 ns" { irrecv:inst2|always1~174 irrecv:inst2|always1~175 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.206 ns) 3.447 ns irrecv:inst2\|Selector7~376 5 COMB LCCOMB_X20_Y6_N18 1 " "Info: 5: + IC(0.390 ns) + CELL(0.206 ns) = 3.447 ns; Loc. = LCCOMB_X20_Y6_N18; Fanout = 1; COMB Node = 'irrecv:inst2\|Selector7~376'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.596 ns" { irrecv:inst2|always1~175 irrecv:inst2|Selector7~376 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.206 ns) 4.036 ns irrecv:inst2\|Selector7~377 6 COMB LCCOMB_X20_Y6_N0 1 " "Info: 6: + IC(0.383 ns) + CELL(0.206 ns) = 4.036 ns; Loc. = LCCOMB_X20_Y6_N0; Fanout = 1; COMB Node = 'irrecv:inst2\|Selector7~377'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.589 ns" { irrecv:inst2|Selector7~376 irrecv:inst2|Selector7~377 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.544 ns) 4.953 ns irrecv:inst2\|Selector7~378 7 COMB LCCOMB_X20_Y6_N30 1 " "Info: 7: + IC(0.373 ns) + CELL(0.544 ns) = 4.953 ns; Loc. = LCCOMB_X20_Y6_N30; Fanout = 1; COMB Node = 'irrecv:inst2\|Selector7~378'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.917 ns" { irrecv:inst2|Selector7~377 irrecv:inst2|Selector7~378 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.061 ns irrecv:inst2\|RecvState.STARTDOWN 8 REG LCFF_X20_Y6_N31 2 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 5.061 ns; Loc. = LCFF_X20_Y6_N31; Fanout = 2; REG Node = 'irrecv:inst2\|RecvState.STARTDOWN'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { irrecv:inst2|Selector7~378 irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.658 ns ( 52.52 % ) " "Info: Total cell delay = 2.658 ns ( 52.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.403 ns ( 47.48 % ) " "Info: Total interconnect delay = 2.403 ns ( 47.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.061 ns" { irrecv:inst2|TimerCnt[0] irrecv:inst2|RecvState~311 irrecv:inst2|always1~174 irrecv:inst2|always1~175 irrecv:inst2|Selector7~376 irrecv:inst2|Selector7~377 irrecv:inst2|Selector7~378 irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.061 ns" { irrecv:inst2|TimerCnt[0] {} irrecv:inst2|RecvState~311 {} irrecv:inst2|always1~174 {} irrecv:inst2|always1~175 {} irrecv:inst2|Selector7~376 {} irrecv:inst2|Selector7~377 {} irrecv:inst2|Selector7~378 {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.485ns 0.391ns 0.381ns 0.390ns 0.383ns 0.373ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.319ns 0.206ns 0.206ns 0.544ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.061 ns" { irrecv:inst2|TimerCnt[0] irrecv:inst2|RecvState~311 irrecv:inst2|always1~174 irrecv:inst2|always1~175 irrecv:inst2|Selector7~376 irrecv:inst2|Selector7~377 irrecv:inst2|Selector7~378 irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.061 ns" { irrecv:inst2|TimerCnt[0] {} irrecv:inst2|RecvState~311 {} irrecv:inst2|always1~174 {} irrecv:inst2|always1~175 {} irrecv:inst2|Selector7~376 {} irrecv:inst2|Selector7~377 {} irrecv:inst2|Selector7~378 {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.485ns 0.391ns 0.381ns 0.390ns 0.383ns 0.373ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.319ns 0.206ns 0.206ns 0.544ns 0.108ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk~0 register irrecv:inst2\|DataGet\[19\] register irrecv:inst2\|DataGet\[19\] 499 ps " "Info: Minimum slack time is 499 ps for clock \"clk~0\" between source register \"irrecv:inst2\|DataGet\[19\]\" and destination register \"irrecv:inst2\|DataGet\[19\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns irrecv:inst2\|DataGet\[19\] 1 REG LCFF_X18_Y6_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y6_N17; Fanout = 2; REG Node = 'irrecv:inst2\|DataGet\[19\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns irrecv:inst2\|DataGet\[19\]~2578 2 COMB LCCOMB_X18_Y6_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X18_Y6_N16; Fanout = 1; COMB Node = 'irrecv:inst2\|DataGet\[19\]~2578'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { irrecv:inst2|DataGet[19] irrecv:inst2|DataGet[19]~2578 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns irrecv:inst2\|DataGet\[19\] 3 REG LCFF_X18_Y6_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X18_Y6_N17; Fanout = 2; REG Node = 'irrecv:inst2\|DataGet\[19\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { irrecv:inst2|DataGet[19]~2578 irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { irrecv:inst2|DataGet[19] irrecv:inst2|DataGet[19]~2578 irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { irrecv:inst2|DataGet[19] {} irrecv:inst2|DataGet[19]~2578 {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.203 ns " "Info: + Latch edge is -2.203 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Destination clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.203 ns " "Info: - Launch edge is -2.203 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Source clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 destination 5.942 ns + Longest register " "Info: + Longest clock path from clock \"clk~0\" to destination register is 5.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 5.942 ns irrecv:inst2\|DataGet\[19\] 5 REG LCFF_X18_Y6_N17 2 " "Info: 5: + IC(0.820 ns) + CELL(0.666 ns) = 5.942 ns; Loc. = LCFF_X18_Y6_N17; Fanout = 2; REG Node = 'irrecv:inst2\|DataGet\[19\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.53 % ) " "Info: Total cell delay = 1.636 ns ( 27.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.306 ns ( 72.47 % ) " "Info: Total interconnect delay = 4.306 ns ( 72.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 source 5.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk~0\" to source register is 5.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 5.942 ns irrecv:inst2\|DataGet\[19\] 5 REG LCFF_X18_Y6_N17 2 " "Info: 5: + IC(0.820 ns) + CELL(0.666 ns) = 5.942 ns; Loc. = LCFF_X18_Y6_N17; Fanout = 2; REG Node = 'irrecv:inst2\|DataGet\[19\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.53 % ) " "Info: Total cell delay = 1.636 ns ( 27.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.306 ns ( 72.47 % ) " "Info: Total interconnect delay = 4.306 ns ( 72.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { irrecv:inst2|DataGet[19] irrecv:inst2|DataGet[19]~2578 irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { irrecv:inst2|DataGet[19] {} irrecv:inst2|DataGet[19]~2578 {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|DataGet[19] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.942 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|DataGet[19] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.820ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}