prev_cmp_seg7led.tan.qmsg

来自「FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "irrecv:inst2\|ClkDevideOut " "Info: Detected ripple clock \"irrecv:inst2\|ClkDevideOut\" as buffer" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } } { "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "irrecv:inst2\|ClkDevideOut" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}