decoder15_test.v

用verilog编写的bch译码器

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   08:40:05 05/14/2008
// Design Name:   decoder15
// Module Name:   D:/luoqiwu/FPGA/oytt/decoder15_test.v
// Project Name:  oytt
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: decoder15
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module decoder15_test_v;

	// Inputs
	reg clk;
	reg [14:0] r;

	// Outputs
	wire [14:0] c;

	// Instantiate the Unit Under Test (UUT)
	decoder15 uut (
		.clk(clk), 
		.r(r), 
		.c(c)
	);
	
	initial begin
	  		forever #25 clk=!clk;
	end
	
	initial begin
		// Initialize Inputs
		clk = 0;
		r = 0;

		// Wait 100 ns for global reset to finish
		#200;
      r=15'b0000_1000_0001_000;
		// Add stimulus here

	end
      
endmodule