cycloneiii_3c25_start_niosii_standard_sopc.ptf.pre_generation_ptf
来自「nios里面用自定义指令集来实现三角函数」· PRE_GENERATION_PTF 代码 · 共 2,216 行 · 第 1/5 页
PRE_GENERATION_PTF
2,216 行
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Has_Clock = "0";
Is_Bridge = "1";
}
}
MODULE pipeline_bridge_peripherals
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_address
{
type = "address";
width = "6";
direction = "input";
Is_Enabled = "1";
}
PORT s1_nativeaddress
{
type = "nativeaddress";
width = "6";
direction = "input";
Is_Enabled = "1";
}
PORT s1_burstcount
{
type = "burstcount";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT s1_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT s1_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT s1_endofpacket
{
type = "endofpacket";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT s1_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT s1_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT s1_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "256";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "3";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "6";
Opaque_Bridges_To = "m1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x08000000";
}
Base_Address = "0x08000000";
}
}
MASTER m1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "8";
Opaque_Bridges_To = "s1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
}
PORT_WIRING
{
PORT m1_address
{
type = "address";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT m1_nativeaddress
{
type = "nativeaddress";
width = "6";
direction = "output";
Is_Enabled = "1";
}
PORT m1_burstcount
{
type = "burstcount";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m1_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT m1_chipselect
{
type = "chipselect";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m1_debugaccess
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m1_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m1_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT m1_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT m1_endofpacket
{
type = "endofpacket";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT m1_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT m1_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT m1_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry jtag_uart/avalon_jtag_slave
{
address = "0x00000080";
span = "0x00000008";
}
Entry button_pio/s1
{
address = "0x00000060";
span = "0x00000010";
}
Entry sys_clk_timer/s1
{
address = "0x00000000";
span = "0x00000020";
}
Entry high_res_timer/s1
{
address = "0x00000020";
span = "0x00000020";
}
Entry led_pio/s1
{
address = "0x00000070";
span = "0x00000010";
}
Entry sysid/control_slave
{
address = "0x00000088";
span = "0x00000008";
}
Entry sys_pll/s1
{
address = "0x00000040";
span = "0x00000020";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Is_Downstream = "1";
Is_Upstream = "1";
Is_Waitrequest = "1";
Enable_Arbiterlock = "0";
}
class = "altera_avalon_pipeline_bridge";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "system_clk";
Has_Clock = "1";
}
}
MODULE jtag_uart
{
SLAVE avalon_jtag_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
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