cycloneiii_3c25_start_niosii_standard_sopc.ptf.pre_generation_ptf
来自「nios里面用自定义指令集来实现三角函数」· PRE_GENERATION_PTF 代码 · 共 2,216 行 · 第 1/5 页
PRE_GENERATION_PTF
2,216 行
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_init_done
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT reset_phy_clk_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT global_reset_n
{
type = "export";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT phy_clk
{
type = "out_clk";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
}
PORT local_write_req
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_read_req
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_burstbegin
{
type = "beginbursttransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_ready
{
type = "waitrequest_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_rdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT local_rdata_valid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_wdata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT local_be
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT local_size
{
type = "burstcount";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_request_n
{
type = "resetrequest_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "33554432";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "32";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "23";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Clock_Source = "altmemddr_phy_clk_out";
Has_Clock = "1";
MASTERED_BY altmemddr_bridge/m1
{
priority = "8";
Offset_Address = "0x00000000";
}
Base_Address = "0x02000000";
}
}
iss_model_name = "altera_memory";
class = "ddr_high_perf";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "Cyclone III";
datawidth = "16";
memtype = "DDR SDRAM";
local_burst_length = "1";
num_chipselects = "1";
cas_latency = "3.0";
addr_width = "23";
ba_width = "2";
row_width = "13";
col_width = "9";
clockspeed = "9090";
data_width_ratio = "2";
reg_dimm = "false";
dq_per_dqs = "8";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Clock_Source = "osc_clk";
Has_Clock = "1";
}
class_version = "7.2";
}
MODULE altmemddr_bridge
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT slave_address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
}
PORT slave_nativeaddress
{
type = "nativeaddress";
width = "23";
direction = "input";
Is_Enabled = "1";
}
PORT slave_read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT slave_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT slave_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT slave_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT slave_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT slave_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT slave_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "33554432";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "48";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "23";
Opaque_Bridges_To = "m1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Clock_Source = "system_clk";
Has_Clock = "1";
MASTERED_BY cpu/data_master
{
priority = "8";
Offset_Address = "0x02000000";
}
MASTERED_BY cpu/instruction_master
{
priority = "8";
Offset_Address = "0x02000000";
}
Base_Address = "0x02000000";
}
}
MASTER m1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT master_address
{
type = "address";
width = "25";
direction = "output";
Is_Enabled = "1";
}
PORT master_nativeaddress
{
type = "nativeaddress";
width = "23";
direction = "output";
Is_Enabled = "1";
}
PORT master_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT master_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT master_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT master_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT master_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT master_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT master_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "25";
Opaque_Bridges_To = "s1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Clock_Source = "altmemddr_phy_clk_out";
Has_Clock = "1";
}
MEMORY_MAP
{
Entry altmemddr/s1
{
address = "0x00000000";
span = "0x02000000";
}
}
}
class = "altera_avalon_clock_crossing";
class_version = "7.2";
iss_model_name = "altera_avalon_clock_crossing";
WIZARD_SCRIPT_ARGUMENTS
{
Upstream_FIFO_Depth = "64";
Downstream_FIFO_Depth = "8";
Data_Width = "32";
Native_Address_Width = "23";
Use_Byte_Enable = "1";
Use_Burst_Count = "0";
Maximum_Burst_Size = "8";
Upstream_Use_Register = "0";
Downstream_Use_Register = "0";
Device_Family = "CYCLONEIII";
}
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