prev_cmp_timer.qmsg

能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能

{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } { { "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } { { "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" {  } { { "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "iclk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node iclk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:hou\[4\] " "Info: Destination node DTIMER:U1\|\\F:hou\[4\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:hou[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:hou[4] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:hou\[3\] " "Info: Destination node DTIMER:U1\|\\F:hou\[3\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:hou[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:hou[3] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:min\[5\] " "Info: Destination node DTIMER:U1\|\\F:min\[5\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[5] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:min\[4\] " "Info: Destination node DTIMER:U1\|\\F:min\[4\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[4] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:min\[3\] " "Info: Destination node DTIMER:U1\|\\F:min\[3\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[3] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:min\[2\] " "Info: Destination node DTIMER:U1\|\\F:min\[2\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:sec\[5\] " "Info: Destination node DTIMER:U1\|\\F:sec\[5\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[5] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:sec\[4\] " "Info: Destination node DTIMER:U1\|\\F:sec\[4\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[4] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:sec\[3\] " "Info: Destination node DTIMER:U1\|\\F:sec\[3\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[3] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DTIMER:U1\|\\F:sec\[2\] " "Info: Destination node DTIMER:U1\|\\F:sec\[2\]" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/quartus72lite/altera/72/quartus/bin/pin_planner.ppl" { iclk } } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "iclk" } } } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DLED:U2\|Mux23~52  " "Info: Automatically promoted node DLED:U2\|Mux23~52 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux23~52 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux23~52 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DLED:U2\|Mux7~52  " "Info: Automatically promoted node DLED:U2\|Mux7~52 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 115 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux7~52 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux7~52 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DLED:U2\|Mux41~23  " "Info: Automatically promoted node DLED:U2\|Mux41~23 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 19 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux41~23 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|Mux41~23 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.151 ns register register " "Info: Estimated most critical path is register to register delay of 4.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DTIMER:U1\|\\F:sec\[2\] 1 REG LAB_X33_Y13 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y13; Fanout = 26; REG Node = 'DTIMER:U1\|\\F:sec\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:sec[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.150 ns) 1.120 ns DTIMER:U1\|Equal1~46 2 COMB LAB_X33_Y14 3 " "Info: 2: + IC(0.970 ns) + CELL(0.150 ns) = 1.120 ns; Loc. = LAB_X33_Y14; Fanout = 3; COMB Node = 'DTIMER:U1\|Equal1~46'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { DTIMER:U1|\F:sec[2] DTIMER:U1|Equal1~46 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.912 ns) + CELL(0.150 ns) 2.182 ns DTIMER:U1\|Equal1~47 3 COMB LAB_X33_Y13 4 " "Info: 3: + IC(0.912 ns) + CELL(0.150 ns) = 2.182 ns; Loc. = LAB_X33_Y13; Fanout = 4; COMB Node = 'DTIMER:U1\|Equal1~47'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { DTIMER:U1|Equal1~46 DTIMER:U1|Equal1~47 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.419 ns) 2.746 ns DTIMER:U1\|\\F:hou\[4\]~188 4 COMB LAB_X33_Y13 5 " "Info: 4: + IC(0.145 ns) + CELL(0.419 ns) = 2.746 ns; Loc. = LAB_X33_Y13; Fanout = 5; COMB Node = 'DTIMER:U1\|\\F:hou\[4\]~188'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { DTIMER:U1|Equal1~47 DTIMER:U1|\F:hou[4]~188 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.660 ns) 4.151 ns DTIMER:U1\|\\F:hou\[2\] 5 REG LAB_X34_Y14 17 " "Info: 5: + IC(0.745 ns) + CELL(0.660 ns) = 4.151 ns; Loc. = LAB_X34_Y14; Fanout = 17; REG Node = 'DTIMER:U1\|\\F:hou\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.405 ns" { DTIMER:U1|\F:hou[4]~188 DTIMER:U1|\F:hou[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.379 ns ( 33.22 % ) " "Info: Total cell delay = 1.379 ns ( 33.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.772 ns ( 66.78 % ) " "Info: Total interconnect delay = 2.772 ns ( 66.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.151 ns" { DTIMER:U1|\F:sec[2] DTIMER:U1|Equal1~46 DTIMER:U1|Equal1~47 DTIMER:U1|\F:hou[4]~188 DTIMER:U1|\F:hou[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X33_Y12 X43_Y23 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y12 to location X43_Y23" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "44 " "Warning: Found 44 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oLSec\[0\] 0 " "Info: Pin \"oLSec\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "oLSec\[1\] 0 " "Info: Pin \"oLSec\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF