prev_cmp_timer.tan.qmsg

能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能

{ "Info" "ITDB_TSU_RESULT" "DTIMER:U1\|\\F:fre\[15\] iRst iclk 5.859 ns register " "Info: tsu for register \"DTIMER:U1\|\\F:fre\[15\]\" (data pin = \"iRst\", clock pin = \"iclk\") is 5.859 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.542 ns + Longest pin register " "Info: + Longest pin to register delay is 8.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns iRst 1 PIN PIN_G26 43 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 43; PIN Node = 'iRst'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iRst } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.020 ns) + CELL(0.660 ns) 8.542 ns DTIMER:U1\|\\F:fre\[15\] 2 REG LCFF_X33_Y12_N19 3 " "Info: 2: + IC(7.020 ns) + CELL(0.660 ns) = 8.542 ns; Loc. = LCFF_X33_Y12_N19; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[15\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.680 ns" { iRst DTIMER:U1|\F:fre[15] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.522 ns ( 17.82 % ) " "Info: Total cell delay = 1.522 ns ( 17.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.020 ns ( 82.18 % ) " "Info: Total interconnect delay = 7.020 ns ( 82.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.542 ns" { iRst DTIMER:U1|\F:fre[15] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.542 ns" { iRst {} iRst~combout {} DTIMER:U1|\F:fre[15] {} } { 0.000ns 0.000ns 7.020ns } { 0.000ns 0.862ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.647 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to destination register is 2.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 33 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 33; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.537 ns) 2.647 ns DTIMER:U1\|\\F:fre\[15\] 3 REG LCFF_X33_Y12_N19 3 " "Info: 3: + IC(0.993 ns) + CELL(0.537 ns) = 2.647 ns; Loc. = LCFF_X33_Y12_N19; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[15\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { iclk~clkctrl DTIMER:U1|\F:fre[15] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 58.03 % ) " "Info: Total cell delay = 1.536 ns ( 58.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.111 ns ( 41.97 % ) " "Info: Total interconnect delay = 1.111 ns ( 41.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[15] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.647 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[15] {} } { 0.000ns 0.000ns 0.118ns 0.993ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.542 ns" { iRst DTIMER:U1|\F:fre[15] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.542 ns" { iRst {} iRst~combout {} DTIMER:U1|\F:fre[15] {} } { 0.000ns 0.000ns 7.020ns } { 0.000ns 0.862ns 0.660ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[15] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.647 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[15] {} } { 0.000ns 0.000ns 0.118ns 0.993ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "iclk oLMin\[7\] DLED:U2\|oLMin\[7\] 13.798 ns register " "Info: tco from clock \"iclk\" to destination pin \"oLMin\[7\]\" through register \"DLED:U2\|oLMin\[7\]\" is 13.798 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 8.045 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to source register is 8.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(0.787 ns) 3.560 ns DTIMER:U1\|\\F:min\[4\] 2 REG LCFF_X32_Y13_N23 26 " "Info: 2: + IC(1.774 ns) + CELL(0.787 ns) = 3.560 ns; Loc. = LCFF_X32_Y13_N23; Fanout = 26; REG Node = 'DTIMER:U1\|\\F:min\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { iclk DTIMER:U1|\F:min[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.410 ns) 4.755 ns DLED:U2\|Mux23~52 3 COMB LCCOMB_X32_Y13_N12 1 " "Info: 3: + IC(0.785 ns) + CELL(0.410 ns) = 4.755 ns; Loc. = LCCOMB_X32_Y13_N12; Fanout = 1; COMB Node = 'DLED:U2\|Mux23~52'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.195 ns" { DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.795 ns) + CELL(0.000 ns) 6.550 ns DLED:U2\|Mux23~52clkctrl 4 COMB CLKCTRL_G12 13 " "Info: 4: + IC(1.795 ns) + CELL(0.000 ns) = 6.550 ns; Loc. = CLKCTRL_G12; Fanout = 13; COMB Node = 'DLED:U2\|Mux23~52clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.795 ns" { DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.345 ns) + CELL(0.150 ns) 8.045 ns DLED:U2\|oLMin\[7\] 5 REG LCCOMB_X35_Y13_N0 2 " "Info: 5: + IC(1.345 ns) + CELL(0.150 ns) = 8.045 ns; Loc. = LCCOMB_X35_Y13_N0; Fanout = 2; REG Node = 'DLED:U2\|oLMin\[7\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[7] } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.346 ns ( 29.16 % ) " "Info: Total cell delay = 2.346 ns ( 29.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.699 ns ( 70.84 % ) " "Info: Total interconnect delay = 5.699 ns ( 70.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.045 ns" { iclk DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[7] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.045 ns" { iclk {} iclk~combout {} DTIMER:U1|\F:min[4] {} DLED:U2|Mux23~52 {} DLED:U2|Mux23~52clkctrl {} DLED:U2|oLMin[7] {} } { 0.000ns 0.000ns 1.774ns 0.785ns 1.795ns 1.345ns } { 0.000ns 0.999ns 0.787ns 0.410ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.753 ns + Longest register pin " "Info: + Longest register to pin delay is 5.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DLED:U2\|oLMin\[7\] 1 REG LCCOMB_X35_Y13_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X35_Y13_N0; Fanout = 2; REG Node = 'DLED:U2\|oLMin\[7\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DLED:U2|oLMin[7] } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.121 ns) + CELL(2.632 ns) 5.753 ns oLMin\[7\] 2 PIN PIN_Y23 0 " "Info: 2: + IC(3.121 ns) + CELL(2.632 ns) = 5.753 ns; Loc. = PIN_Y23; Fanout = 0; PIN Node = 'oLMin\[7\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.753 ns" { DLED:U2|oLMin[7] oLMin[7] } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 45.75 % ) " "Info: Total cell delay = 2.632 ns ( 45.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.121 ns ( 54.25 % ) " "Info: Total interconnect delay = 3.121 ns ( 54.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.753 ns" { DLED:U2|oLMin[7] oLMin[7] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "5.753 ns" { DLED:U2|oLMin[7] {} oLMin[7] {} } { 0.000ns 3.121ns } { 0.000ns 2.632ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.045 ns" { iclk DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[7] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.045 ns" { iclk {} iclk~combout {} DTIMER:U1|\F:min[4] {} DLED:U2|Mux23~52 {} DLED:U2|Mux23~52clkctrl {} DLED:U2|oLMin[7] {} } { 0.000ns 0.000ns 1.774ns 0.785ns 1.795ns 1.345ns } { 0.000ns 0.999ns 0.787ns 0.410ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.753 ns" { DLED:U2|oLMin[7] oLMin[7] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "5.753 ns" { DLED:U2|oLMin[7] {} oLMin[7] {} } { 0.000ns 3.121ns } { 0.000ns 2.632ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DTIMER:U1\|\\F:fre\[20\] iRst iclk -4.934 ns register " "Info: th for register \"DTIMER:U1\|\\F:fre\[20\]\" (data pin = \"iRst\", clock pin = \"iclk\") is -4.934 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.658 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to destination register is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 33 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 33; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 2.658 ns DTIMER:U1\|\\F:fre\[20\] 3 REG LCFF_X33_Y14_N15 3 " "Info: 3: + IC(1.004 ns) + CELL(0.537 ns) = 2.658 ns; Loc. = LCFF_X33_Y14_N15; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[20\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { iclk~clkctrl DTIMER:U1|\F:fre[20] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.79 % ) " "Info: Total cell delay = 1.536 ns ( 57.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.122 ns ( 42.21 % ) " "Info: Total interconnect delay = 1.122 ns ( 42.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.658 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[20] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.658 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[20] {} } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.858 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns iRst 1 PIN PIN_G26 43 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 43; PIN Node = 'iRst'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iRst } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.336 ns) + CELL(0.660 ns) 7.858 ns DTIMER:U1\|\\F:fre\[20\] 2 REG LCFF_X33_Y14_N15 3 " "Info: 2: + IC(6.336 ns) + CELL(0.660 ns) = 7.858 ns; Loc. = LCFF_X33_Y14_N15; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[20\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.996 ns" { iRst DTIMER:U1|\F:fre[20] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.522 ns ( 19.37 % ) " "Info: Total cell delay = 1.522 ns ( 19.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.336 ns ( 80.63 % ) " "Info: Total interconnect delay = 6.336 ns ( 80.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { iRst DTIMER:U1|\F:fre[20] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.858 ns" { iRst {} iRst~combout {} DTIMER:U1|\F:fre[20] {} } { 0.000ns 0.000ns 6.336ns } { 0.000ns 0.862ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.658 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[20] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.658 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[20] {} } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.858 ns" { iRst DTIMER:U1|\F:fre[20] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lit