prev_cmp_timer.tan.qmsg

能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iclk register DTIMER:U1\|\\F:fre\[3\] register DTIMER:U1\|\\F:hou\[2\] 194.7 MHz 5.136 ns Internal " "Info: Clock \"iclk\" has Internal fmax of 194.7 MHz between source register \"DTIMER:U1\|\\F:fre\[3\]\" and destination register \"DTIMER:U1\|\\F:hou\[2\]\" (period= 5.136 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.926 ns + Longest register register " "Info: + Longest register to register delay is 4.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DTIMER:U1\|\\F:fre\[3\] 1 REG LCFF_X34_Y13_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y13_N13; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[3\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:fre[3] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.456 ns) + CELL(0.371 ns) 1.827 ns DTIMER:U1\|Equal0~275 2 COMB LCCOMB_X33_Y13_N6 1 " "Info: 2: + IC(1.456 ns) + CELL(0.371 ns) = 1.827 ns; Loc. = LCCOMB_X33_Y13_N6; Fanout = 1; COMB Node = 'DTIMER:U1\|Equal0~275'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.827 ns" { DTIMER:U1|\F:fre[3] DTIMER:U1|Equal0~275 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.242 ns) + CELL(0.150 ns) 2.219 ns DTIMER:U1\|Equal0~276 3 COMB LCCOMB_X33_Y13_N2 1 " "Info: 3: + IC(0.242 ns) + CELL(0.150 ns) = 2.219 ns; Loc. = LCCOMB_X33_Y13_N2; Fanout = 1; COMB Node = 'DTIMER:U1\|Equal0~276'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.392 ns" { DTIMER:U1|Equal0~275 DTIMER:U1|Equal0~276 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.393 ns) 2.876 ns DTIMER:U1\|Equal0~277 4 COMB LCCOMB_X33_Y13_N22 21 " "Info: 4: + IC(0.264 ns) + CELL(0.393 ns) = 2.876 ns; Loc. = LCCOMB_X33_Y13_N22; Fanout = 21; COMB Node = 'DTIMER:U1\|Equal0~277'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { DTIMER:U1|Equal0~276 DTIMER:U1|Equal0~277 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.393 ns) 3.554 ns DTIMER:U1\|\\F:hou\[4\]~188 5 COMB LCCOMB_X33_Y13_N10 5 " "Info: 5: + IC(0.285 ns) + CELL(0.393 ns) = 3.554 ns; Loc. = LCCOMB_X33_Y13_N10; Fanout = 5; COMB Node = 'DTIMER:U1\|\\F:hou\[4\]~188'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.678 ns" { DTIMER:U1|Equal0~277 DTIMER:U1|\F:hou[4]~188 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.712 ns) + CELL(0.660 ns) 4.926 ns DTIMER:U1\|\\F:hou\[2\] 6 REG LCFF_X34_Y14_N23 17 " "Info: 6: + IC(0.712 ns) + CELL(0.660 ns) = 4.926 ns; Loc. = LCFF_X34_Y14_N23; Fanout = 17; REG Node = 'DTIMER:U1\|\\F:hou\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.372 ns" { DTIMER:U1|\F:hou[4]~188 DTIMER:U1|\F:hou[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.967 ns ( 39.93 % ) " "Info: Total cell delay = 1.967 ns ( 39.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.959 ns ( 60.07 % ) " "Info: Total interconnect delay = 2.959 ns ( 60.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.926 ns" { DTIMER:U1|\F:fre[3] DTIMER:U1|Equal0~275 DTIMER:U1|Equal0~276 DTIMER:U1|Equal0~277 DTIMER:U1|\F:hou[4]~188 DTIMER:U1|\F:hou[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "4.926 ns" { DTIMER:U1|\F:fre[3] {} DTIMER:U1|Equal0~275 {} DTIMER:U1|Equal0~276 {} DTIMER:U1|Equal0~277 {} DTIMER:U1|\F:hou[4]~188 {} DTIMER:U1|\F:hou[2] {} } { 0.000ns 1.456ns 0.242ns 0.264ns 0.285ns 0.712ns } { 0.000ns 0.371ns 0.150ns 0.393ns 0.393ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.658 ns + Shortest register " "Info: + Shortest clock path from clock \"iclk\" to destination register is 2.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 33 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 33; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 2.658 ns DTIMER:U1\|\\F:hou\[2\] 3 REG LCFF_X34_Y14_N23 17 " "Info: 3: + IC(1.004 ns) + CELL(0.537 ns) = 2.658 ns; Loc. = LCFF_X34_Y14_N23; Fanout = 17; REG Node = 'DTIMER:U1\|\\F:hou\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { iclk~clkctrl DTIMER:U1|\F:hou[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.79 % ) " "Info: Total cell delay = 1.536 ns ( 57.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.122 ns ( 42.21 % ) " "Info: Total interconnect delay = 1.122 ns ( 42.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.658 ns" { iclk iclk~clkctrl DTIMER:U1|\F:hou[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.658 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:hou[2] {} } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 2.654 ns - Longest register " "Info: - Longest clock path from clock \"iclk\" to source register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 33 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 33; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.654 ns DTIMER:U1\|\\F:fre\[3\] 3 REG LCFF_X34_Y13_N13 3 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X34_Y13_N13; Fanout = 3; REG Node = 'DTIMER:U1\|\\F:fre\[3\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { iclk~clkctrl DTIMER:U1|\F:fre[3] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.87 % ) " "Info: Total cell delay = 1.536 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[3] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.658 ns" { iclk iclk~clkctrl DTIMER:U1|\F:hou[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.658 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:hou[2] {} } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[3] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.926 ns" { DTIMER:U1|\F:fre[3] DTIMER:U1|Equal0~275 DTIMER:U1|Equal0~276 DTIMER:U1|Equal0~277 DTIMER:U1|\F:hou[4]~188 DTIMER:U1|\F:hou[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "4.926 ns" { DTIMER:U1|\F:fre[3] {} DTIMER:U1|Equal0~275 {} DTIMER:U1|Equal0~276 {} DTIMER:U1|Equal0~277 {} DTIMER:U1|\F:hou[4]~188 {} DTIMER:U1|\F:hou[2] {} } { 0.000ns 1.456ns 0.242ns 0.264ns 0.285ns 0.712ns } { 0.000ns 0.371ns 0.150ns 0.393ns 0.393ns 0.660ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.658 ns" { iclk iclk~clkctrl DTIMER:U1|\F:hou[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.658 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:hou[2] {} } { 0.000ns 0.000ns 0.118ns 1.004ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:fre[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:fre[3] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "iclk 186 " "Warning: Circuit may not operate. Detected 186 non-operational path(s) clocked by clock \"iclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DTIMER:U1\|\\F:min\[0\] DLED:U2\|oLMin\[2\] iclk 3.097 ns " "Info: Found hold time violation between source  pin or register \"DTIMER:U1\|\\F:min\[0\]\" and destination pin or register \"DLED:U2\|oLMin\[2\]\" for clock \"iclk\" (Hold time is 3.097 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.373 ns + Largest " "Info: + Largest clock skew is 5.373 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 8.027 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to destination register is 8.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(0.787 ns) 3.560 ns DTIMER:U1\|\\F:min\[4\] 2 REG LCFF_X32_Y13_N23 26 " "Info: 2: + IC(1.774 ns) + CELL(0.787 ns) = 3.560 ns; Loc. = LCFF_X32_Y13_N23; Fanout = 26; REG Node = 'DTIMER:U1\|\\F:min\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { iclk DTIMER:U1|\F:min[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.785 ns) + CELL(0.410 ns) 4.755 ns DLED:U2\|Mux23~52 3 COMB LCCOMB_X32_Y13_N12 1 " "Info: 3: + IC(0.785 ns) + CELL(0.410 ns) = 4.755 ns; Loc. = LCCOMB_X32_Y13_N12; Fanout = 1; COMB Node = 'DLED:U2\|Mux23~52'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.195 ns" { DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.795 ns) + CELL(0.000 ns) 6.550 ns DLED:U2\|Mux23~52clkctrl 4 COMB CLKCTRL_G12 13 " "Info: 4: + IC(1.795 ns) + CELL(0.000 ns) = 6.550 ns; Loc. = CLKCTRL_G12; Fanout = 13; COMB Node = 'DLED:U2\|Mux23~52clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.795 ns" { DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.150 ns) 8.027 ns DLED:U2\|oLMin\[2\] 5 REG LCCOMB_X38_Y13_N14 1 " "Info: 5: + IC(1.327 ns) + CELL(0.150 ns) = 8.027 ns; Loc. = LCCOMB_X38_Y13_N14; Fanout = 1; REG Node = 'DLED:U2\|oLMin\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[2] } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.346 ns ( 29.23 % ) " "Info: Total cell delay = 2.346 ns ( 29.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.681 ns ( 70.77 % ) " "Info: Total interconnect delay = 5.681 ns ( 70.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.027 ns" { iclk DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.027 ns" { iclk {} iclk~combout {} DTIMER:U1|\F:min[4] {} DLED:U2|Mux23~52 {} DLED:U2|Mux23~52clkctrl {} DLED:U2|oLMin[2] {} } { 0.000ns 0.000ns 1.774ns 0.785ns 1.795ns 1.327ns } { 0.000ns 0.999ns 0.787ns 0.410ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 2.654 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to source register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 11; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 33 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 33; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "TIMER.vhd" "" { Text "D:/timer/TIMER.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.654 ns DTIMER:U1\|\\F:min\[0\] 3 REG LCFF_X33_Y13_N31 22 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X33_Y13_N31; Fanout = 22; REG Node = 'DTIMER:U1\|\\F:min\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { iclk~clkctrl DTIMER:U1|\F:min[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.87 % ) " "Info: Total cell delay = 1.536 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:min[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:min[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.027 ns" { iclk DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.027 ns" { iclk {} iclk~combout {} DTIMER:U1|\F:min[4] {} DLED:U2|Mux23~52 {} DLED:U2|Mux23~52clkctrl {} DLED:U2|oLMin[2] {} } { 0.000ns 0.000ns 1.774ns 0.785ns 1.795ns 1.327ns } { 0.000ns 0.999ns 0.787ns 0.410ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:min[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:min[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.026 ns - Shortest register register " "Info: - Shortest register to register delay is 2.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DTIMER:U1\|\\F:min\[0\] 1 REG LCFF_X33_Y13_N31 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y13_N31; Fanout = 22; REG Node = 'DTIMER:U1\|\\F:min\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DTIMER:U1|\F:min[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.376 ns) 1.187 ns DLED:U2\|Mux18~156 2 COMB LCCOMB_X37_Y13_N14 1 " "Info: 2: + IC(0.811 ns) + CELL(0.376 ns) = 1.187 ns; Loc. = LCCOMB_X37_Y13_N14; Fanout = 1; COMB Node = 'DLED:U2\|Mux18~156'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { DTIMER:U1|\F:min[0] DLED:U2|Mux18~156 } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.438 ns) 2.026 ns DLED:U2\|oLMin\[2\] 3 REG LCCOMB_X38_Y13_N14 1 " "Info: 3: + IC(0.401 ns) + CELL(0.438 ns) = 2.026 ns; Loc. = LCCOMB_X38_Y13_N14; Fanout = 1; REG Node = 'DLED:U2\|oLMin\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { DLED:U2|Mux18~156 DLED:U2|oLMin[2] } "NODE_NAME" } } { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.814 ns ( 40.18 % ) " "Info: Total cell delay = 0.814 ns ( 40.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.212 ns ( 59.82 % ) " "Info: Total interconnect delay = 1.212 ns ( 59.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.026 ns" { DTIMER:U1|\F:min[0] DLED:U2|Mux18~156 DLED:U2|oLMin[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.026 ns" { DTIMER:U1|\F:min[0] {} DLED:U2|Mux18~156 {} DLED:U2|oLMin[2] {} } { 0.000ns 0.811ns 0.401ns } { 0.000ns 0.376ns 0.438ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "DLED.vhd" "" { Text "D:/timer/DLED.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.027 ns" { iclk DTIMER:U1|\F:min[4] DLED:U2|Mux23~52 DLED:U2|Mux23~52clkctrl DLED:U2|oLMin[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.027 ns" { iclk {} iclk~combout {} DTIMER:U1|\F:min[4] {} DLED:U2|Mux23~52 {} DLED:U2|Mux23~52clkctrl {} DLED:U2|oLMin[2] {} } { 0.000ns 0.000ns 1.774ns 0.785ns 1.795ns 1.327ns } { 0.000ns 0.999ns 0.787ns 0.410ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { iclk iclk~clkctrl DTIMER:U1|\F:min[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DTIMER:U1|\F:min[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.026 ns" { DTIMER:U1|\F:min[0] DLED:U2|Mux18~156 DLED:U2|oLMin[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.026 ns" { DTIMER:U1|\F:min[0] {} DLED:U2|Mux18~156 {} DLED:U2|oLMin[2] {} } { 0.000ns 0.811ns 0.401ns } { 0.000ns 0.376ns 0.438ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}