display_control.v

一个LCD控制器的verilog源代码

module display_control(
						GCLK,
						DISPLAY_DATA,
						DISPLAY_MODE,DISPLAY_RD,DISPLAY_WR,DISPLAY_CS,
						SRAM1_DATA,SRAM1_A,SRAM1_WEN,SRAM1_CEN,
						SRAM2_DATA,SRAM2_A,SRAM2_WEN,SRAM2_CEN,
						LCD_R,LCD_G,LCD_B,LCD_R0,LCD_B0,
						LCD_CK,LCD_HYSNC,LCD_VSYNC,
						LCD_ENABLE,LCD_RL,LCD_UD
						//test_bus
						);
	input GCLK;
	//signals from DSP
	input [4:0] DISPLAY_MODE;
	input DISPLAY_RD,DISPLAY_WR,DISPLAY_CS;
	input [15:0] DISPLAY_DATA;
	//signals to/from SRAM1 & SRAM2
	output [18:0] SRAM1_A,SRAM2_A;
	inout [15:0] SRAM1_DATA,SRAM2_DATA;
	output SRAM1_WEN,SRAM1_CEN,SRAM2_WEN,SRAM2_CEN;
	//signals to LCD
	output [5:1] LCD_R,LCD_B;
	output LCD_R0,LCD_B0;
	output [5:0] LCD_G;
	output LCD_CK,LCD_HYSNC,LCD_VSYNC;
	output LCD_ENABLE,LCD_RL,LCD_UD;
	//test pin
	//output [13:0] test_bus;
	
	reg SRAM1_WEN,SRAM2_WEN;
	
	reg [5:1] LCD_R,LCD_B;
	reg [5:0] LCD_G;
	reg LCD_HYSNC,LCD_VSYNC;
	reg LCD_ENABLE;
		
	reg [15:0] TRANSPARENT_COLOR;
	
	reg div2_CLK;
	wire SRAM_CLK;
	reg LCD_CLK;
	wire reset;
	reg [9:0] H_counter,V_counter;
	reg a_line_ok,a_screen_ok;
	reg screen_data_en;
	reg RGB_data_en;
	reg [15:0] temp_RGB_data;

	reg [15:0] buffer_SRAM1_DATA,buffer_SRAM2_DATA;
	reg [15:0] reg_SRAM1_DATA,reg_SRAM2_DATA;    
	
	reg [18:0] Read_Add;
	reg [18:0] Write_Add;

	reg [18:0] X_Add;
	reg [8:0] Y_Add;
	reg [18:0] start_point_position;
	reg [15:0] DSP_data_buffer;
	wire DSP_write_SRAM_finish;
	reg DSP_write_data_ready;
	
	reg show_red1,show_red;

	assign reset =DISPLAY_CS;

	/*--- 系统时钟 --*/
	/*reg div2_clk;
	always @(posedge GCLK)
		div2_clk <=~div2_clk;*/	
	assign SRAM_CLK =GCLK;
	always @(posedge SRAM_CLK)  //LCD clock
		LCD_CLK <=~LCD_CLK;

	/*--- LCD signals ---*/
	assign LCD_RL =1;
	assign LCD_UD =0;

	assign LCD_CK =LCD_CLK;   //LCD 工作时钟

	//行控制信号
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			H_counter <=0;
		else if(a_line_ok==1)
			H_counter <=0;
		else
			H_counter <=H_counter + 1;		
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			a_line_ok <=1;
		else if(H_counter==770)
			a_line_ok <=1;
		else
			a_line_ok <=0;
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			LCD_HYSNC <=1;
		else if(a_line_ok==1)
			LCD_HYSNC <=0;
		else if(H_counter==7)
			LCD_HYSNC <=1;
	//LCD enable signal
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			LCD_ENABLE <=0;
		else if(H_counter==50)
			LCD_ENABLE <=1;
		else if(H_counter==689)
			LCD_ENABLE <=0;	
	//场控制信号
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			V_counter <=0;
		else if(a_screen_ok==1)
			V_counter <=0;
		else if(a_line_ok==1)
			V_counter <=V_counter + 1;
	
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			a_screen_ok <=1;
		else if(V_counter==515)
			a_screen_ok <=1;
		else
			a_screen_ok <=0;

	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			LCD_VSYNC <=1;
		else if(a_screen_ok==1)
			LCD_VSYNC <=0;
		else if(V_counter==3)
			LCD_VSYNC <=1;
	//RGB数据控制信号		
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			screen_data_en <=0;
		else if(V_counter==34)
			screen_data_en <=1;
		else if(V_counter==515)
			screen_data_en <=0;	
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			RGB_data_en <=0;
		else if(H_counter==47) //????
			RGB_data_en <=1;
		else if(H_counter==687) //???
			RGB_data_en <=0;	
	always @(posedge LCD_CLK or negedge reset)
		if(~reset)
			Read_Add <=0;
		else if(screen_data_en==0)
			Read_Add <=0;
		else if(RGB_data_en==1)
			Read_Add <=Read_Add + 1;
			
	reg display_lay2;
	always @(buffer_SRAM1_DATA or TRANSPARENT_COLOR)
		if(buffer_SRAM1_DATA==TRANSPARENT_COLOR)
			display_lay2 =1;
		else
			display_lay2 =0;
	always @(posedge LCD_CLK)
		case(display_lay2)
			1'b1: temp_RGB_data <=buffer_SRAM2_DATA;
			1'b0: temp_RGB_data <=buffer_SRAM1_DATA;
		endcase
	
	always @(posedge LCD_CLK)
		if((screen_data_en==0) || (RGB_data_en==0))
			begin 
				LCD_R <=0;LCD_G <=0;LCD_B <=0;
			end
		else
			begin
				LCD_R <=temp_RGB_data[4:0];
				LCD_G <=temp_RGB_data[10:5];
				LCD_B <=temp_RGB_data[15:11];
			end
		  
	assign LCD_R0 =0;
	assign LCD_B0 =0;
			
	/*--- SRAM interface ---*/
	assign SRAM1_CEN =0;
	assign SRAM2_CEN =0;
	
	always @(posedge SRAM_CLK or negedge reset)
		if(~reset)
			SRAM1_WEN <=1;
	  	else if((DISPLAY_MODE[4]==1) & (DSP_write_data_ready==1) & (LCD_CLK==0))
			SRAM1_WEN <=0;
		else 
			SRAM1_WEN <=1;
	always @(posedge SRAM_CLK or negedge reset)
		if(~reset)
			SRAM2_WEN <=1;
	  	else if((DISPLAY_MODE[4]==0) & (DSP_write_data_ready==1) & (LCD_CLK==0))
			SRAM2_WEN <=0;
		else 
			SRAM2_WEN <=1;
				
	assign SRAM1_A =(SRAM1_WEN==1) ? Read_Add : Write_Add;
	assign SRAM2_A =(SRAM2_WEN==1) ? Read_Add : Write_Add;
	
	assign SRAM1_DATA =(SRAM1_WEN==0) ? DISPLAY_DATA : 16'bzzzzzzzzzzzzzzzz;
	assign SRAM2_DATA =(SRAM2_WEN==0) ? DISPLAY_DATA : 16'bzzzzzzzzzzzzzzzz;
		
		
	always @(posedge LCD_CLK)
		buffer_SRAM1_DATA <=SRAM1_DATA;
	always @(posedge LCD_CLK)
		buffer_SRAM2_DATA <=SRAM2_DATA;

   	/*--- DSP interface ---*/
	//DISPLAY_CS=0 ---> 初始化:TRANSPARENT_COLOR
	//DISPLAY_CS=1 ---> 开始显示
	//-----DISPLAY_MODE[4:0]
	//-----5'b1xxxx -> 写SRAM1，即第一层；
	//-----5'b0xxxx -> 写SRAM2，即第二层；
	//-----X,Y Start position: [0,0]
	//-----5'bx0001 -> 写X坐标；
	//-----5'bx0010 -> 写Y坐标；
	//-----5'bx0011 -> 水平方向连续写RGB值；
	//-----5'bx0000 -> 垂直方向连续写RGB值；
	
	always @(posedge DISPLAY_CS)
		TRANSPARENT_COLOR <=DISPLAY_DATA;
		
	always @(posedge DISPLAY_WR)
		case(DISPLAY_MODE[1:0])
			2'b00: Y_Add =Y_Add + 1;
			2'b01: X_Add =DISPLAY_DATA[9:0];
			2'b10: Y_Add =DISPLAY_DATA[8:0];
			2'b11: X_Add =X_Add + 1;
		endcase
			
	wire [18:0] multi_result;
	 my_multi my_multi1(
					.dataa(Y_Add),
					.result(multi_result));
	always @(X_Add or multi_result)
		start_point_position =multi_result + X_Add;
	
	always @(posedge DISPLAY_WR or negedge reset)
   		if(~reset)
			Write_Add <=0;
		else if((SRAM1_WEN==1) & (SRAM2_WEN==1))
			Write_Add <=start_point_position;
			
	assign DSP_write_SRAM_finish =SRAM1_WEN & SRAM2_WEN;
	always @(posedge DISPLAY_WR or negedge DSP_write_SRAM_finish)
   		if(DSP_write_SRAM_finish==0)
			DSP_write_data_ready <=0;
		else if((DISPLAY_MODE[1:0]==2'b00) || (DISPLAY_MODE[1:0]==2'b11)) 
	   		DSP_write_data_ready <=1;
endmodule