ring.txt

来自「用于打铃系统的vhdl实现的源码」· 文本 代码 · 共 66 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ring IS
 PORT(RESET:      IN STD_LOGIC;
      SCLK:       IN STD_LOGIC;
      FREQ:       IN STD_LOGIC;
      ALARM:      OUT STD_LOGIC;             --dirve signal for the bell
      light:      OUT STD_LOGIC;
      hourhdis:   IN INTEGER RANGE 0 TO 2;   --time information recieved from module of "clock"
      hourldis:   IN INTEGER RANGE 0 TO 9;
      minhdis:    IN INTEGER RANGE 0 TO 5;
      minldis:    IN INTEGER RANGE 0 TO 9;
      sechdis:    IN INTEGER RANGE 0 TO 5;
      secldis:    IN INTEGER RANGE 0 TO 9);
 END ring;
ARCHITECTURE archi OF ring IS
   BEGIN
   PROCESS(secldis)
    BEGIN
    IF reset='1' THEN
          ALARM<='0';
    ELSIF (minhdis=5 and minldis=9 and sechdis=5 and secldis=0 and FREQ='1') OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=2 and FREQ='1') OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=4 and FREQ='1') OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=6 and FREQ='1') OR
          (minhdis=5 and minldis=9 and sechdis=5 and secldis=8 and FREQ='1') OR
          (minhdis=0 and minldis=0 and sechdis=0 and secldis=0 and SCLK='1') THEN
          ALARM<='1';
    ELSE  ALARM<='0';
    END IF;
    IF reset='1' THEN
     light<='0';
    ELSIF (hourhdis=0 and hourldis=8 and minhdis=3 and minldis=0)  THEN
           light<='1';
    ELSE light<='0'; 
    END IF;
 END PROCESS;
END archi;
 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY freq IS
 PORT(A:IN  std_logic;
      B:OUT std_logic);
END freq;
ARCHITECTURE freq_arc OF freq IS
 SIGNAL cnt1:std_logic;
BEGIN
 PROCESS(A)
  VARIABLE cnt:INTEGER RANGE 0 TO 512;
  CONSTANT modulus:INTEGER:=200;
 BEGIN
  IF (A'EVENT AND A='1') then
   IF cnt=modulus then
      cnt:=0;cnt1<=NOT cnt1;B<=cnt1;
   END IF;
   cnt:=cnt+1;
  END IF;
 END PROCESS;
END freq_arc;