fp.vhd

多功能数字时钟设计方案及电路图

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp is
	port(inclk :in std_logic;
		 fpa  :out std_logic;
		 fpb  :out std_logic;
		 fpc :out std_logic
		);
end fp;
architecture behav of fp is
    signal mda    :std_logic_vector(14 downto 0);
	signal mdb	  :std_logic_vector(9 downto 0);
	signal mdc	  :std_logic_vector(2 downto 0);
	signal fpa1,fpb1,fpc1:std_logic;
begin
	process(inclk)
		begin
			if(inclk'event and inclk='1')then
				if mda=24999 then
					mda<=(others=>'0');
					fpa1<=not fpa1;
				else
					mda<=mda+1;
				end if;
			end if;
		fpa<=fpa1;
	end process;
		 process(fpa1,inclk)
			begin
				if(fpa1'event and fpa1='1')then
					if mdb=499 then
						mdb<=(others=>'0');
						fpb1<=not fpb1;
					else
						mdb<=mdb+1;
					end if;
				end if;
		fpb<=fpb1;
		end process;
		 process(fpa1,inclk)
			begin
				if(fpa1'event and fpa1='1')then
					if mdc=4 then
						mdc<=(others=>'0');
						fpc1<=not fpc1;
					else
						mdc<=mdc+1;
					end if;
				end if;
		fpc<=fpc1;
		end process;
end behav;