adjuster.vhd

多功能数字时钟设计方案及电路图

Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity adjuster is
	port(
		  inclk: in std_logic;
		  set  : in std_logic;
		  mode : in std_logic;
		  En   : in std_logic;
		  clk  : out std_logic;
		  s_count:in std_logic;
		  m_count:in std_logic;
		  s_en   :out std_logic;
		  m_en   :out std_logic;
		  h_en   :out std_logic;
		  mm_en  :out std_logic;
		  conver :out std_logic;
		  flag   :out std_logic
		 );
end adjuster;

architecture behav of adjuster is
	signal sel    : std_logic;
	signal s_reg  : std_logic;
	signal m_reg  : std_logic;
	signal h_reg  : std_logic;
	signal flag1  : std_logic;
	signal mm_reg : std_logic;
	signal conver12:std_logic;
	signal con    : integer range 0 to 4 :=0;
  begin
   process(mode,set)
	begin
		if rising_edge(mode) then
		    if con=4 then
				con<=0;
			else
				con<=con+1;
			end if;
		end if;
   end process;

   process(con)
	begin
	 case con is
		when 0=> sel<='1';
				 s_reg<='0';
				 m_reg<='0';
				 h_reg<='0';
				 mm_reg<='0';
				 conver12<='1';
				 flag<='1';
		when 1=> sel<='0';
				 s_reg<='1';
				 m_reg<='0';
				 h_reg<='0';
				 mm_reg<='0';
				 flag<='0';
				 conver12<='1';
		when 2=> sel<='0';
				 s_reg<='0';
				 m_reg<='1';
				 h_reg<='0';
				 mm_reg<='0';
				 conver12<='1';
				 flag<='0';
		when 3=> sel<='0';
				 s_reg<='0';
				 m_reg<='0';
				 h_reg<='1';
				 mm_reg<='0';
				 conver12<='1';
				 flag<='0';
		when 4=> sel<='1';
				 s_reg<='0';
				 m_reg<='0';
				 h_reg<='0';
				 mm_reg<='0';
				 conver12<='0';
				 flag<='1';
		when others=> sel<='1';
				 s_reg<='0';
				 m_reg<='0';
				 h_reg<='0';
				 mm_reg<='0';
				 conver12<='1';
				 flag<='1';
     end case;
   end process;
	

	process(sel)
	 begin

		case sel is
			when '0'=> s_en<=s_reg;
					   m_en<=m_reg;
					   h_en<=h_reg;
					   mm_en<=mm_reg;
			           clk <=set;
					   conver<=conver12;
			when '1'=> s_en<=En;
					   m_en<=s_count;
					   h_en<=m_count;
					   mm_en<=En;
					   clk <=inclk;
					   conver<=conver12;
			when others=> s_en<=En;
					   m_en<=s_count;
					   h_en<=m_count;
					   clk <=inclk;
					   mm_en<=En;
					   conver<=conver12;
       end case;
   end process;
end behav;