map.tcl

hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档

define_design_lib WORK -path ../work
#---------------------------------------------
#set library
#----------------------------------------------
source ./set_lib.tcl
#report_lib -all > ../rpt/report_lib.rpt

#-------------------------------------------------
#             Synopsys Switches            
#-------------------------------------------------
#/*get rid of tri-state declarations and assigns*/
set verilogout_no_tri true
set verilogout_equation false

#/*enable if def processing*/
set hdlin_enable_vpp true

#/*enable inferred latch warnings*/
set hdlin_check_no_latch true

#/*disable skew for feedback loops*/
set timing_self_loops_no_skew true

#/*clock gating control*/
#set power_cg_flatten true
#set power_hdlc_do_not_split_cg_cells "false"
#set power_preserve_rtl_hier_names true
#set hdlin_no_group_register "true"

#------------------------------------------------
# Map Design
#------------------------------------------------
source ./analyze.tcl
elaborate hdlc_recv
current_design hdlc_recv

link
#write -f db -h -o ../out/Filter.unmapped.hier.db

#set_port_is_pad {iModeTest iClkTest inRstTest iScanIn iScanEn oScanOut iClk inRst oData oClk}
#insert_pads
source ./constraints.tcl
#set_clock_gating_style -sequential latch
#insert_clock_gating
check_design > ../rpt/check_design.rpt
write_script -format dctcl -output ../out/hdlc_recv.sdc

uniquify
#propagate_constraints -gate_clock
set_fix_multiple_port_nets -all -buffer_constants
compile -map_effort medium 
#write -f db -h -o ../out/Filter.map.hier.db
#write -f verilog -h -o ../out/Filter.map.hier.v
set_fix_hold $CLK_PORT
ungroup -all -flatten
compile -inc
source ./dft.tcl
compile -scan 
write -f db -h -o ../out/hdlc_recv.db
write -f verilog -h -o ../out/hdlc_recv.v

#--------------------------------------------------
#report
#--------------------------------------------------
report_clock > ../rpt/report_clock.rpt
report_design > ../rpt/report_design.rpt
report_constraint -all_violators > ../rpt/report_constraint.rpt
#report_timing -nworst 5
report_timing -path  full_clock -cap -tran -net -delay max -nworst 5 > ../rpt/max_timing.rpt
report_timing -path  full_clock -cap -tran -net -delay min > ../rpt/min_timing.rpt
report_area > ../rpt/report_area.rpt
report_power > ../rpt/report_power.rpt
report_net_fanout -threshold 50 > ../rpt/hign_fanout.rpt
quit