command.log

hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档

#@ set target_library  your_library.db
#@ set synthetic_library  ""
#@ set command_log_file  "./command.log"
#@ set designer  ""
#@ set company  ""
#@ set find_converts_name_lists  "false"
#@ 
#@ set symbol_library  your_library.sdb 
#@ 
#@ # Turn on Formality SVF recording
#@ if { $synopsys_program_name == "dc_shell"      ||      $synopsys_program_name == "design_vision" ||      $synopsys_program_name == "fpga_shell"    ||      $synopsys_program_name == "fpga_vision" } {
#@   set_svf -default default.svf
#@ }
#@ 
#@ # from the Schematic Variable Group 
#@ 
#@ # from the Plot Variable Group 
#@ if { $sh_arch == "hp700" } {
#@   set plot_command "lp -d" 
#@ } else {
#@   set plot_command "lpr -Plw" 
#@ }
#@ 
#@ set view_command_log_file  "./view_command.log"
#@ 
#@ # from the View Variable group
#@ if { $sh_arch == "hp700" } {
#@    set text_print_command  "lp -d" 
#@ } else {
#@    set text_print_command  "lpr -Plw" 
#@ }
#@ #
#@ #       System Variable Group:
#@ #
#@ #       These variables are system-wide variables.
#@ #
#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid
#@ set auto_link_disable  "false"
#@ set auto_link_options  "-all"
#@ set uniquify_naming_style  "%s_%d"
#@ set verbose_messages  "true"
#@ set echo_include_commands  "true"
#@ set svf_file_records_change_names_changes "true"
#@ set change_names_update_inst_tree   "true"
#@ set change_names_dont_change_bus_members false
#@ set default_name_rules ""
#@ #set tdrc_enable_clock_table_creation   "true"
#@ 
#@ #
#@ #       Compile Variable Group:
#@ #
#@ #       These variables affect the designs created by the COMPILE command.
#@ #
#@ set compile_assume_fully_decoded_three_state_busses   "false"
#@ set compile_no_new_cells_at_top_level   "false"
#@ set compile_dont_touch_annotated_cell_during_inplace_opt   "false"
#@ set compile_update_annotated_delays_during_inplace_opt  "true"
#@ set compile_instance_name_prefix   "U"
#@ set compile_instance_name_suffix   ""
#@ set compile_negative_logic_methodology   "false"
#@ set compile_disable_hierarchical_inverter_opt   "false"
#@ set compile_use_fast_delay_mode   "true"
#@ set compile_use_low_timing_effort   "false"
#@ set compile_fix_cell_degradation   "false"
#@ set compile_preserve_subdesign_interfaces   "false"
#@ set port_complement_naming_style   "%s_BAR"
#@ set compile_implementation_selection   "true"
#@ set compile_create_mux_op_hierarchy   "false"
#@ set compile_delete_unloaded_sequential_cells   "true"
#@ set reoptimize_design_changed_list_file_name   ""
#@ set compile_checkpoint_phases "false"
#@ set compile_cpu_limit 0.0
#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";
#@ set compile_top_all_paths   "false"
#@ set compile_top_acs_partition "false"
#@ set default_port_connection_class "universal"
#@ set compile_hold_reduce_cell_count "false"
#@ set compile_retime_license_behavior "wait"
#@ set dont_touch_nets_with_size_only_cells "false"
#@ set suppress_errors  {PWR-18 OPT-932 OPT-317}
#@ 
#@ set compile_new_scan_flow false
#@ 
#@ #
#@ # Variable(s) to control the behavior of the optimize_registers command
#@ #
#@ set optimize_reg_always_insert_sequential false 
#@ set optimize_reg_max_time_borrow -1048576.0
#@ set optimize_reg_enable_clock_gating_latches false
#@ 
#@ group_variable retiming optimize_reg_always_insert_sequential
#@ group_variable retiming optimize_reg_max_time_borrow
#@ group_variable retiming optimize_reg_enable_clock_gating_latches
#@ 
#@ 
#@ set ldd_return_val 0
#@ if { [string compare $dc_shell_mode "default"] == 0 } {
#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh
#@   alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "
#@ 
#@ }
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl
#@   alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "
#@ }
#@ 
#@ 
#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";
#@ 
#@ set compile_top_all_paths "false"
#@ alias compile_inplace_changed_list_file_name                 reoptimize_design_changed_list_file_name
#@ 
#@ #
#@ #  These variables affects compile, report_timing and report_constraints
#@ #  commands.
#@ #
#@ set enable_recovery_removal_arcs  "false"
#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net}
#@ 
#@ #
#@ #       Multibit Variable Group:
#@ #
#@ #       These variables affect the multibit mapping functionality
#@ #
#@ 
#@ set bus_multiple_separator_style  ","
#@ 
#@ #
#@ #       ILM Variable Group:
#@ #
#@ #       These variables affect Interface Logic Model functionality
#@ #
#@ 
#@ set ilm_ignore_percentage 25
#@ 
#@ #
#@ #       Estimator Variable Group:
#@ #
#@ #       These variables affect the designs created by the ESTIMATE command.
#@ #
#@ set estimate_resource_preference  "fast"
#@ alias est_resource_preference estimate_resource_preference
#@ set lbo_lfo_enable_at_pin_count   3
#@ set lbo_cells_in_regions   "false"
#@ 
#@ #     Synthetic Library Group:
#@ #
#@ #       These variable affect synthetic library processing.
#@ #
#@ set cache_dir_chmod_octal   "777"
#@ set cache_file_chmod_octal  "666"
#@ set cache_read   "~"
#@ set cache_read_info  "false"
#@ set cache_write  "~"
#@ set cache_write_info   "false"
#@ set mgi_scratch_directory "designware_generator"
#@ set synlib_dont_get_license  {}
#@ set synlib_library_list   {DW01 DW02 DW03 DW04 DW05 DW06 DW07}
#@ set synlib_model_map_effort  "medium"
#@ set synlib_wait_for_design_license {}
#@ 
#@ #
#@ #       Insert_DFT Variable Group:
#@ #
#@ #set test_default_client_order [list]
#@ set test_point_keep_hierarchy "false" 
#@ set test_use_test_models "false"
#@ set insert_dft_clean_up "true"
#@ set insert_test_design_naming_style  "%s_test_%d"
#@ # /*insert_test_scan_chain_only_one_clock = "false"
#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/
#@ set test_clock_port_naming_style  "test_c%s"
#@ set test_scan_clock_a_port_naming_style  "test_sca%s"
#@ set test_scan_clock_b_port_naming_style  "test_scb%s"
#@ set test_scan_clock_port_naming_style   "test_sc%s"
#@ set test_scan_enable_inverted_port_naming_style   "test_sei%s"
#@ set test_scan_enable_port_naming_style   "test_se%s"
#@ set test_scan_in_port_naming_style   "test_si%s%s"
#@ set test_scan_out_port_naming_style  "test_so%s%s"
#@ set test_non_scan_clock_port_naming_style  "test_nsc_%s"
#@ set test_default_min_fault_coverage  95
#@ set test_dedicated_subdesign_scan_outs  "false"
#@ set test_disable_find_best_scan_out  "false"
#@ set test_dont_fix_constraint_violations  "false"
#@ set test_isolate_hier_scan_out  0
#@ set test_mode_port_naming_style  "test_mode%s"
#@ set test_mode_port_inverted_naming_style  "test_mode_i%s"
#@ set compile_dont_use_dedicated_scanout 1
#@ set test_mux_constant_so "false"
#@ set test_mux_constant_si "false"
#@ 
#@ #
#@ #        Analyze_Scan Variable Group:
#@ #
#@ #     These variables affect the designs created by the PREVIEW_SCAN command.
#@ #
#@ set test_preview_scan_shows_cell_types  "false"
#@ set test_scan_link_so_lockup_key "l"
#@ set test_scan_link_wire_key  "w"
#@ set test_scan_segment_key  "s"
#@ set test_scan_true_key  "t"
#@ set test_jump_over_bufs_invs "true"
#@ 
#@ #
#@ #        bsd Variable Group:
#@ 
#@ #        These variables affect the report generated by the check_bsd command
#@ #        and the BSDLout generated by the write_bsdl command.
#@ #
#@ set test_user_test_data_register_naming_style  "UTDR%d"
#@ 
#@ set test_user_defined_instruction_naming_style  "USER%d"
#@ 
#@ set test_bsdl_default_suffix_name  "bsdl"
#@ 
#@ set test_bsdl_max_line_length  80
#@ 
#@ set test_cc_ir_masked_bits 0
#@ 
#@ set test_cc_ir_value_of_masked_bits 0
#@ 
#@ set test_bsd_allow_tolerable_violations "false" 
#@ set test_bsd_optimize_control_cell "false" 
#@ set test_bsd_control_cell_drive_limit 0
#@ set test_bsd_manufacturer_id 0
#@ set test_bsd_part_number 0
#@ set test_bsd_version_number 0
#@ set bsd_max_in_switching_limit 60000
#@ set bsd_max_out_switching_limit 60000
#@ 
#@ #
#@ #        TestManager Variable Group:
#@ #
#@ #        These variables affect the TestManager methodology.
#@ #
#@ set multi_pass_test_generation  "false"
#@ 
#@ #
#@ #        TestSim Variable Group:
#@ #
#@ #        These variables affect the TestSim behavior.
#@ #
#@ # set testsim_print_stats_file  "true"
#@ 
#@ #      Test DRC Variable Group:
#@ #
#@ #        These variables affect the check_test command.
#@ # 
#@ set test_capture_clock_skew  "small_skew"
#@ set test_allow_clock_reconvergence  "true"
#@ set test_check_port_changes_in_capture  "true"
#@ set test_infer_slave_clock_pulse_after_capture "infer"
#@ 
#@ #
#@ #       Test Variable Group:
#@ #
#@ #       These variables affect the rtldrc, check_test, write_test_protocol
#@ #       and write_test command.
#@ #
#@ set test_default_delay  5.0
#@ set test_default_bidir_delay  55.0
#@ set test_default_strobe  95.0
#@ set test_default_strobe_width  0.0
#@ set test_default_period  100.0
#@ set test_default_scan_style  "multiplexed_flip_flop"
#@ set test_stil_netlist_format "db"
#@ set test_stil_multiclock_capture_procedures "false"
#@ set test_stil_max_line_length 72 
#@ set test_write_four_cycle_stil_protocol "false"
#@ set test_protocol_add_cycle "true"
#@ set test_rtldrc_latch_check_style "default"
#@ set test_enable_capture_checks "true"
#@ set ctldb_use_old_prot_flow "false"
#@ 
#@ #
#@ #       Write_Test Variable Group:
#@ #
#@ #       These variables affect output of the WRITE_TEST command.
#@ #
#@ set write_test_input_dont_care_value  "X"
#@ set write_test_vector_file_naming_style  "%s_%d.%s"
#@ set write_test_scan_check_file_naming_style   "%s_schk.%s"
#@ set write_test_pattern_set_naming_style  "TC_Syn_%d"
#@ set write_test_max_cycles  0
#@ set write_test_max_scan_patterns  0
#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */
#@ set write_test_formats   {synopsys tssi_ascii tds verilog vhdl wgl}
#@ set write_test_include_scan_cell_info  "true"
#@ set write_test_round_timing_values "true"
#@ set write_test_new_translation_engine "false"
#@ 
#@ #
#@ #       Schematic and EDIF and Hdl Variable Groups:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command, define the behavior of the
#@ #       DC system EDIF interface, and are for controlling hdl
#@ #       reading.
#@ #
#@ set bus_dimension_separator_style  {][}
#@ set bus_naming_style  {%s[%d]}
#@ 
#@ 
#@ #
#@ #       Schematic and EDIF Variable Groups:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command and define the behavior of
#@ #       the DC system EDIF interface.
#@ #
#@ set bus_range_separator_style  ":"
#@ 
#@ 
#@ #
#@ # EDIF and Io Variable Groups:
#@ #
#@ # These variables define the behavior of the DC system EDIF interface and
#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.
#@ 
#@ set bus_inference_descending_sort  "true"
#@ set bus_inference_style  ""
#@ set write_name_nets_same_as_ports  "false"
#@ #
#@ #       Schematic Variable Group:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command.
#@ #
#@ set font_library  "1_25.font"
#@ set generic_symbol_library  "generic.sdb"
#@ set gen_max_ports_on_symbol_side  0
#@ set duplicate_ports   "false"
#@