urat.vhd

VHDL语言编写的全功能串口模块（包含DTR

                        END IF; 
               WHEN "0010" =>  --发送第2位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "0011" =>  --发送第3位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "0100" => --发送第4位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
 
 
  
 
 
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                         END IF; 
               WHEN "0101" => --发送第5位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "0110" => --发送第6位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "0111" => --发送第7位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "1000" =>  --发送第8位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= txd_buf(0);     
                           txd_buf(6 DOWNTO 0) <= txd_buf(7 DOWNTO 1);     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "1001" =>  --发送停止位 
                        IF (clkbaud_tras = '1') THEN 
                           txd_reg <= '1';     
                           txd_buf <= "01010101";     
                           state_tras <= state_tras + "0001";     
                        END IF; 
               WHEN "1111" => 
                        IF (clkbaud_tras = '1') THEN 
                           state_tras <= state_tras + "0001";     
                           send_state <= send_state + "001";     
                           trasstart <= '0';     
                           CASE send_state IS 
                              WHEN "000" => 
                                       txd_buf <= "01100101"; --"e"    
                              WHEN "001" => 
                                       txd_buf <= "01101100"; --"l"    
                              WHEN "010" => 
                                       txd_buf <= "01100011";  --"c"   
                              WHEN "011" => 
                                       txd_buf <= "01101111"; --"o"   
                              WHEN "100" => 
                                       txd_buf <= "01101101";  --"m"   
                              WHEN "101" => 
                                       txd_buf <= "01100101";-- "e"    
                              WHEN OTHERS  => 
                                       txd_buf <= "01100101";   
                               
                           END CASE; 

                        END IF; 

               WHEN OTHERS  => 
                        IF (clkbaud_tras = '1') THEN 
                           state_tras <= state_tras + "0001";     
                           trasstart <= '1';     
 
 
    
 
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                         END IF; 
                
            END CASE;
 
         END IF; 
      END IF; 
END IF; 
   END PROCESS; 

   PROCESS(clkbaud8x,rst)  --接受PC机的数据 
   BEGIN 
      IF (NOT rst = '1') THEN 
         rxd_reg1 <= '0';     
         rxd_reg2 <= '0';     
         rxd_buf <= "00000000";     
         state_rec <= "0000";     
         recstart <= '0';     
         recstart_tmp <= '0';     
      ELSE IF(clkbaud8x'EVENT AND clkbaud8x = '1') THEN 
         rxd_reg1 <= rxd;     
         rxd_reg2 <= rxd_reg1;     
         IF (state_rec = "0000") THEN 
            IF (recstart_tmp = '1') THEN 
               recstart <= '1';     
               recstart_tmp <= '0';     
               state_rec <= state_rec + "0001";     
            ELSE 
               IF ((NOT rxd_reg1 AND rxd_reg2) = '1') THEN --检测到起始位的下降沿，进入接受状态 
                  recstart_tmp <= '1';     
               END IF; 
            END IF; 
         ELSE 
            IF (state_rec >= "0001" AND state_rec<="1000") THEN 
               IF (clkbaud_rec = '1') THEN 
                  rxd_buf(7) <= rxd_reg2;     
                  rxd_buf(6 DOWNTO 0) <= rxd_buf(7 DOWNTO 1);     
                  state_rec <= state_rec + "0001";     
               END IF; 
            ELSE 
               IF (state_rec = "1001") THEN 
                  IF (clkbaud_rec = '1') THEN 
                     state_rec <= "0000";     
                     recstart <= '0';     
                  END IF; 
               END IF; 
            END IF; 
         END IF; 
      END IF; 
END IF; 
   END PROCESS; 

   PROCESS(rxd_buf)   --将接受的数据用数码管显示出来 
   BEGIN 
      CASE rxd_buf IS 
         WHEN "00110000" => 
                  seg_data <= "00000011";     
         WHEN "00110001" => 
                  seg_data <= "10011111";     
         WHEN "00110010" => 
                  seg_data <= "00100101";     
         WHEN "00110011" => 
                  seg_data <= "00001101";     
         WHEN "00110100" => 
                  seg_data <= "10011001";     
         WHEN "00110101" => 
                  seg_data <= "01001001";     
         WHEN "00110110" => 
                  seg_data <= "01000001";     
         WHEN "00110111" => 
                  seg_data <= "00011111";     
         WHEN "00111000" => 
                  seg_data <= "00000001";     
         WHEN "01000001" => 
                  seg_data <= "00011001";     
         WHEN "01000010" => 
                  seg_data <= "00010001";     
         WHEN "01000011" => 
                  seg_data <= "11000001";     
         WHEN "01000100" => 
                  seg_data <= "01100011";     
         WHEN "01000101" => 
                  seg_data <= "10000101";     
         WHEN "01000110" => 
                  seg_data <= "01100001";     
         WHEN "01000111" => 
                  seg_data <= "01110001";     
         WHEN OTHERS  => 
                  seg_data <= "01110110";     
       
      END CASE; 
   END PROCESS; 

END arch;