urat.tan.rpt

VHDL语言编写的全功能串口模块（包含DTR

+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To          ; From Clock ;
+-------+--------------+------------+------------+-------------+------------+
; N/A   ; None         ; 17.994 ns  ; txd_buf[7] ; out_data[7] ; clk        ;
; N/A   ; None         ; 17.970 ns  ; txd_buf[2] ; out_data[2] ; clk        ;
; N/A   ; None         ; 17.566 ns  ; txd_buf[1] ; out_data[1] ; clk        ;
; N/A   ; None         ; 17.289 ns  ; txd_buf[0] ; out_data[0] ; clk        ;
; N/A   ; None         ; 17.218 ns  ; txd_buf[3] ; out_data[3] ; clk        ;
; N/A   ; None         ; 16.937 ns  ; txd_buf[4] ; out_data[4] ; clk        ;
; N/A   ; None         ; 16.926 ns  ; txd_buf[5] ; out_data[5] ; clk        ;
; N/A   ; None         ; 16.889 ns  ; txd_buf[6] ; out_data[6] ; clk        ;
; N/A   ; None         ; 16.858 ns  ; txd_reg    ; txd         ; clk        ;
; N/A   ; None         ; 13.420 ns  ; clkbaud8x  ; clkout      ; clk        ;
+-------+--------------+------------+------------+-------------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+-----------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To            ; To Clock ;
+---------------+-------------+-----------+-----------+---------------+----------+
; N/A           ; None        ; 4.393 ns  ; key_input ; txd_reg       ; clk      ;
; N/A           ; None        ; 4.203 ns  ; key_input ; txd_buf[5]    ; clk      ;
; N/A           ; None        ; 4.201 ns  ; key_input ; txd_buf[4]    ; clk      ;
; N/A           ; None        ; 3.792 ns  ; key_input ; state_tras[2] ; clk      ;
; N/A           ; None        ; 3.774 ns  ; key_input ; state_tras[3] ; clk      ;
; N/A           ; None        ; 3.774 ns  ; key_input ; state_tras[1] ; clk      ;
; N/A           ; None        ; 3.774 ns  ; key_input ; state_tras[0] ; clk      ;
; N/A           ; None        ; 3.713 ns  ; key_input ; txd_buf[0]    ; clk      ;
; N/A           ; None        ; 3.713 ns  ; key_input ; txd_buf[1]    ; clk      ;
; N/A           ; None        ; 3.713 ns  ; key_input ; txd_buf[2]    ; clk      ;
; N/A           ; None        ; 3.547 ns  ; key_input ; txd_buf[3]    ; clk      ;
; N/A           ; None        ; 3.534 ns  ; key_input ; txd_buf[7]    ; clk      ;
; N/A           ; None        ; 3.420 ns  ; key_input ; send_state[0] ; clk      ;
; N/A           ; None        ; 3.418 ns  ; key_input ; trasstart     ; clk      ;
; N/A           ; None        ; 3.416 ns  ; key_input ; txd_buf[6]    ; clk      ;
; N/A           ; None        ; 2.610 ns  ; key_input ; send_state[2] ; clk      ;
; N/A           ; None        ; 2.608 ns  ; key_input ; send_state[1] ; clk      ;
+---------------+-------------+-----------+-----------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Fri Mar 23 21:47:16 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off urat -c urat --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clkbaud8x" as buffer
Info: Clock "clk" has Internal fmax of 211.33 MHz between source register "state_tras[1]" and destination register "txd_buf[0]" (period= 4.732 ns)
    Info: + Longest register to register delay is 4.471 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N7; Fanout = 21; REG Node = 'state_tras[1]'
        Info: 2: + IC(1.320 ns) + CELL(0.590 ns) = 1.910 ns; Loc. = LC_X20_Y12_N3; Fanout = 3; COMB Node = 'trasstart~688'
        Info: 3: + IC(0.438 ns) + CELL(0.442 ns) = 2.790 ns; Loc. = LC_X20_Y12_N4; Fanout = 5; COMB Node = 'txd_buf[0]~1264'
        Info: 4: + IC(0.814 ns) + CELL(0.867 ns) = 4.471 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf[0]'
        Info: Total cell delay = 1.899 ns ( 42.47 % )
        Info: Total interconnect delay = 2.572 ns ( 57.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 12.247 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'
            Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf[0]'
            Info: Total cell delay = 3.121 ns ( 25.48 % )
            Info: Total interconnect delay = 9.126 ns ( 74.52 % )
        Info: - Longest clock path from clock "clk" to source register is 12.247 ns
            Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'
            Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X20_Y11_N7; Fanout = 21; REG Node = 'state_tras[1]'
            Info: Total cell delay = 3.121 ns ( 25.48 % )
            Info: Total interconnect delay = 9.126 ns ( 74.52 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "txd_buf[0]" (data pin = "key_input", clock pin = "clk") i