urat.map.rpt

VHDL语言编写的全功能串口模块（包含DTR

; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; urat.vhd                         ; yes             ; User VHDL File  ; E:/程序/uart/urat.vhd        ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 77    ;
;     -- Combinational with no register       ; 48    ;
;     -- Register only                        ; 8     ;
;     -- Combinational with a register        ; 21    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 37    ;
;     -- 3 input functions                    ; 17    ;
;     -- 2 input functions                    ; 14    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 70    ;
;     -- arithmetic mode                      ; 7     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 6     ;
;     -- asynchronous clear/load mode         ; 29    ;
;                                             ;       ;
; Total registers                             ; 29    ;
; Total logic cells in carry chains           ; 8     ;
; I/O pins                                    ; 15    ;
; Maximum fan-out node                        ; rst   ;
; Maximum fan-out                             ; 29    ;
; Total fan-out                               ; 319   ;
; Average fan-out                             ; 3.47  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |UART                      ; 77 (77)     ; 29           ; 0           ; 0    ; 15   ; 0            ; 48 (48)      ; 8 (8)             ; 21 (21)          ; 8 (8)           ; 0 (0)      ; |UART               ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 2     ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 29    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; txd_reg                                ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 13:1               ; 2 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |UART|txd_buf[4]           ;
; 13:1               ; 3 bits    ; 24 LEs        ; 6 LEs                ; 18 LEs                 ; Yes        ; |UART|txd_buf[0]           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Fri Mar 23 21:47:03 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off urat -c urat
Info: Found 2 design units, including 1 entities, in source file urat.vhd
    Info: Found design unit 1: UART-arch
    Info: Found entity 1: UART
Info: Elaborating entity "uart" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at urat.vhd(62): object "seg_data" assigned a value but never read
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "en" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "rxd"
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 11 output pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Processing ended: Fri Mar 23 21:47:07 2007
    Info: Elapsed time: 00:00:04