urat.qsf

VHDL语言编写的全功能串口模块（包含DTR

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		urat_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C4F324C8
set_global_assignment -name TOP_LEVEL_ENTITY uart
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:02:44  MARCH 23, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 324
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_location_assignment PIN_E14 -to en
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_M10 -to rst
set_location_assignment PIN_C7 -to clk
set_location_assignment PIN_E15 -to rxd
set_location_assignment PIN_F16 -to txd
set_location_assignment PIN_G15 -to key_input
set_location_assignment PIN_G13 -to clkout
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_R11 -to out_data[0]
set_location_assignment PIN_R14 -to out_data[1]
set_location_assignment PIN_U15 -to out_data[2]
set_location_assignment PIN_P12 -to out_data[3]
set_location_assignment PIN_T12 -to out_data[4]
set_location_assignment PIN_V12 -to out_data[5]
set_location_assignment PIN_U11 -to out_data[6]
set_location_assignment PIN_U14 -to out_data[7]
set_global_assignment -name VHDL_FILE urat.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE urat.vwf