mul_normalizer.v

新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方

// This module realizes mormalizer the output 
// to IEEE 754 Standard.
`timescale 1ns/1ps
module mul_normalizer(clk,rst_n,sign_in,zero_in,exp_in,Sum_in,final_out);
input            clk;
input            rst_n;

input  [47:0]    Sum_in;
input            sign_in;
input            zero_in;
input  [8:0]     exp_in;

output [31:0]    final_out;

reg    [24:0]    man_reg;
reg    [8:0]     exp_reg;
reg              sign_reg;
reg              zero_reg;

reg    [8:0]     exp;
reg    [22:0]    man;
reg              sign;

assign           final_out = zero_reg ? 0 : {sign,exp[7:0],man};

always @(posedge clk)
 begin
  if(~ rst_n)
   begin
    man_reg <= 0;
    exp_reg <= 0;
    sign_reg <= 0;
    zero_reg <= 0;
   end
  else
   begin
    man_reg <= Sum_in[47:23];
    exp_reg <= exp_in;
    sign_reg <= sign_in;
    zero_reg <= zero_in;
   end
 end

always @(man_reg or rst_n or sign_reg or exp_reg)
 begin
  if(~ rst_n)
   begin
    sign = 0;
    exp  = 0;
    man  = 0;
   end
  else
   begin
    case(man_reg[24])
     1'b1: begin  // has the carry out  the exp need to add 1.
            exp = exp_reg - 9'b001111110; // -126
            man = man_reg[23:1]; // delete the MSB and the last bit
            sign = sign_reg;
           end
     1'b0: begin
            exp = exp_reg - 9'b001111111; // -127
            man = man_reg[22:0]; // delete the first and second MSB
            sign = sign_reg;
           end
     endcase
    end
   end
endmodule