csa_float_multiplier.v

新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方

//This is the second edition of new_float_multiplier
//In this module,the zero is dealed specially
//This is the top_module of the float_point multiplier system
`timescale 1ns/1ps
module csa_float_multiplier(clk,rst_n,A_in,B_in,final_out);
input                 clk;
input                 rst_n;

//the two float_point inputs
input     [31:0]      A_in;  
input     [31:0]      B_in;

output    [31:0]      final_out;

//wires between selector and multiplier
wire      [23:0]      man_a;
wire      [23:0]      man_b;

//wire between selector2 and exp_reg
wire      [8:0]       exp_wire1;
//wire between selector2 and signreg
wire                  sign_wire1;

//wire between selector2 and zero_reg
wire                  zero_wire1;

//wire between multiplier and normalizer
wire      [47:0]      Sum_wire;

//wire between exp_reg and normalizer2
wire      [8:0]       exp_wire2;
//wire between signreg and normalizer2
wire                  sign_wire2;

//wire between zero_reg and normalizer2
wire                  zero_wire2;

selector M1(.clk(clk),
            .rst_n(rst_n),
            .A_in(A_in),
            .B_in(B_in),
            .man_a(man_a),
            .man_b(man_b),
            .exp_out(exp_wire1),
            .sign(sign_wire1),
            .zero(zero_wire1));

//carrylookahead_multiplier M2(.clk(clk),
              //.rst_n(rst_n),
              //.A_in(man_a),
              //.B_in(man_b),
              //.P(P));
multiply_24bit M2(.clk(clk),
               .rst_n(rst_n),
               .A(man_a),
               .B(man_b),
               .Sum(Sum_wire));

sign_reg       M3(.clk(clk),
              .rst_n(rst_n),
              .sign_in(sign_wire1),
              .sign_out(sign_wire2));

exp_reg        M4(.clk(clk),
              .rst_n(rst_n),
              .exp_in(exp_wire1),
              .exp_out(exp_wire2));

zero_reg      M5(.clk(clk),
             .rst_n(rst_n),
             .zero_in(zero_wire1),
             .zero_out(zero_wire2));

mul_normalizer  M6(.clk(clk),
              .rst_n(rst_n),
              .Sum_in(Sum_wire),
              .sign_in(sign_wire2),
              .exp_in(exp_wire2),
              .zero_in(zero_wire2),
              .final_out(final_out));
endmodule