zero_reg.v

来自「新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方」· Verilog 代码 · 共 30 行

//This module is designed to synchronize zero with
//the output of multiplier
`timescale 1ns/1ps
module zero_reg(clk,rst_n,zero_in,zero_out);
input           clk;
input           rst_n;

input           zero_in;

output          zero_out;

reg             zero_reg;

assign zero_out = zero_reg;

always @(posedge clk)
 begin
  if(~ rst_n)
   begin
    zero_reg <= 0;
    //zero_out <= 0;
   end
  else
   begin
    zero_reg <= zero_in;
    //zero_out <= zero_reg;
   end
  end
endmodule