multiply_24bit.v

新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方

//This module implement the csa multiplier.
//
`timescale 1ns/1ps
module multiply_24bit(clk,rst_n,A,B,Sum);
  input            clk;
  input            rst_n;

	input  [23:0]    A;
	input  [23:0]    B;

	reg    [23:0]    A_reg,B_reg;

	output [47:0]    Sum;

	wire [31:0] P1,P2,P3;

	wire [47:0] s,c;

  always@(posedge clk)
    begin
   	  if(~rst_n)    begin  A_reg <= 0; B_reg <= 0; end
   	  else          begin  A_reg <= A; B_reg <= B; end
    end
 
 csa_mult_8m24 M1(.a(A_reg),.b(B_reg[7:0]),.product(P1));
 
 csa_mult_8m24 M2(.a(A_reg),.b(B_reg[15:8]),.product(P2));
 
 csa_mult_8m24 M3(.a(A_reg),.b(B_reg[23:16]),.product(P3));  //.clk(clk),.rst_n(rst_n),
 
 //assign Sum = {16'b0,P1}+{8'b0,P2,8'b0}+{P3,16'b0};
 
 csa3_48       M4(.a1({16'b0,P1}),.a2({8'b0,P2,8'b0}),.a3({P3,16'b0}),
                  .s(s),.c(c));
 
 assign   Sum = s + {c,1'b0};
 
endmodule

//====================================================================================
`define width  48

module csa3_48(a1,a2,a3,s,c);
  input [`width-1:0] a1,a2,a3;
  output[`width-1:0] s,c;
  
  assign s = a1^a2^a3;
  assign c = (a1&a2)|(a2&a3)|(a1&a3);
endmodule