ibelieve.fit.rpt

<I believe> song _verilog code for any device.

; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/电子/FPGA学习/华清练习/I believe/Ibelieve.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 110 / 5,980 ( 2 % )  ;
;     -- Combinational with no register       ; 46                   ;
;     -- Register only                        ; 0                    ;
;     -- Combinational with a register        ; 64                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 41                   ;
;     -- 3 input functions                    ; 12                   ;
;     -- 2 input functions                    ; 52                   ;
;     -- 1 input functions                    ; 5                    ;
;     -- 0 input functions                    ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 68                   ;
;     -- arithmetic mode                      ; 42                   ;
;     -- qfbk mode                            ; 4                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 18                   ;
;     -- asynchronous clear/load mode         ; 24                   ;
;                                             ;                      ;
; Total registers                             ; 64 / 6,523 ( < 1 % ) ;
; Total LABs                                  ; 14 / 598 ( 2 % )     ;
; Logic elements in carry chains              ; 45                   ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 3 / 185 ( 2 % )      ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )       ;
; Global signals                              ; 4                    ;
; M4Ks                                        ; 0 / 20 ( 0 % )       ;
; Total memory bits                           ; 0 / 92,160 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 92,160 ( 0 % )   ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 4 / 8 ( 50 % )       ;
; Average interconnect usage                  ; 0%                   ;
; Peak interconnect usage                     ; 0%                   ;
; Maximum fan-out node                        ; clk_cnt[23]          ;
; Maximum fan-out                             ; 26                   ;
; Highest non-global fan-out signal           ; Equal0               ;
; Highest non-global fan-out                  ; 15                   ;
; Total fan-out                               ; 454                  ;
; Average fan-out                             ; 3.95                 ;
+---------------------------------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; rst_n   ; 131   ; 3        ; 35           ; 4            ; 2           ; 24                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; sys_clk ; 153   ; 3        ; 35           ; 12           ; 1           ; 24                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                             ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load  ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; sp   ; 62    ; 4        ; 2            ; 0            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 10 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 2 / 44 ( 5 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 48 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 2 / 45 ( 4 % ) ; 3.3V          ; --           ;
; 4        ; 1 / 48 ( 2 % ) ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                       ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                           ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;