ibelieve.map.rpt

<I believe> song _verilog code for any device.

+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                       ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                   ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+
; Ibelieve.v                       ; yes             ; User Verilog HDL File  ; D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Total logic elements                        ; 115         ;
;     -- Combinational with no register       ; 51          ;
;     -- Register only                        ; 5           ;
;     -- Combinational with a register        ; 59          ;
;                                             ;             ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 41          ;
;     -- 3 input functions                    ; 12          ;
;     -- 2 input functions                    ; 52          ;
;     -- 1 input functions                    ; 5           ;
;     -- 0 input functions                    ; 0           ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 73          ;
;     -- arithmetic mode                      ; 42          ;
;     -- qfbk mode                            ; 0           ;
;     -- register cascade mode                ; 0           ;
;     -- synchronous clear/load mode          ; 14          ;
;     -- asynchronous clear/load mode         ; 24          ;
;                                             ;             ;
; Total registers                             ; 64          ;
; Total logic cells in carry chains           ; 45          ;
; I/O pins                                    ; 3           ;
; Maximum fan-out node                        ; clk_cnt[23] ;
; Maximum fan-out                             ; 26          ;
; Total fan-out                               ; 431         ;
; Average fan-out                             ; 3.65        ;
+---------------------------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |Ibelieve                  ; 115 (115)   ; 64           ; 0           ; 3    ; 0            ; 51 (51)      ; 5 (5)             ; 59 (59)          ; 45 (45)         ; 0 (0)      ; |Ibelieve           ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; high[0..3]                            ; Stuck at GND due to stuck port data_in ;
; med[3]                                ; Stuck at GND due to stuck port data_in ;
; low[3]                                ; Stuck at GND due to stuck port data_in ;
; low[1]                                ; Merged with low[2]                     ;
; origin[5]                             ; Merged with origin[9]                  ;
; origin[0]                             ; Merged with origin[4]                  ;
; Total Number of Removed Registers = 9 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 64    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 14    ;
; Number of registers using Asynchronous Clear ; 24    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Jul 16 11:00:41 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Ibelieve -c Ibelieve
Info: Found 1 design units, including 1 entities, in source file Ibelieve.v
    Info: Found entity 1: Ibelieve
Info: Elaborating entity "Ibelieve" for the top level hierarchy
Warning (14130): Reduced register "high[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "high[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "high[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "high[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "med[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "low[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "low[1]" merged to single register "low[2]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "origin[5]" merged to single register "origin[9]"
    Info: Duplicate register "origin[0]" merged to single register "origin[4]"
Info: Implemented 118 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 115 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Allocated 137 megabytes of memory during processing
    Info: Processing ended: Wed Jul 16 11:00:43 2008
    Info: Elapsed time: 00:00:02