prev_cmp_ibelieve.qmsg

<I believe> song _verilog code for any device.

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "173 " "Info: Allocated 173 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 10:56:25 2008 " "Info: Processing ended: Wed Jul 16 10:56:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 16 10:56:27 2008 " "Info: Processing started: Wed Jul 16 10:56:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Ibelieve -c Ibelieve " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Ibelieve -c Ibelieve" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 10:56:29 2008 " "Info: Processing ended: Wed Jul 16 10:56:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 16 10:56:30 2008 " "Info: Processing started: Wed Jul 16 10:56:30 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Ibelieve -c Ibelieve --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Ibelieve -c Ibelieve --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_clk " "Info: Assuming node \"sys_clk\" is an undefined clock" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divider\[13\] " "Info: Detected ripple clock \"divider\[13\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[12\] " "Info: Detected ripple clock \"divider\[12\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[11\] " "Info: Detected ripple clock \"divider\[11\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[10\] " "Info: Detected ripple clock \"divider\[10\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[9\] " "Info: Detected ripple clock \"divider\[9\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[8\] " "Info: Detected ripple clock \"divider\[8\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[7\] " "Info: Detected ripple clock \"divider\[7\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[6\] " "Info: Detected ripple clock \"divider\[6\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[5\] " "Info: Detected ripple clock \"divider\[5\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[23\] " "Info: Detected ripple clock \"clk_cnt\[23\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cnt\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[4\] " "Info: Detected ripple clock \"divider\[4\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[3\] " "Info: Detected ripple clock \"divider\[3\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[2\] " "Info: Detected ripple clock \"divider\[2\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~163 " "Info: Detected gated clock \"Equal0~163\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~163" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~165 " "Info: Detected gated clock \"Equal0~165\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~165" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~166 " "Info: Detected gated clock \"Equal0~166\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~166" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Equal0~164 " "Info: Detected gated clock \"Equal0~164\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "Equal0~164" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[1\] " "Info: Detected ripple clock \"divider\[1\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[2\] " "Info: Detected ripple clock \"clk_cnt\[2\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[0\] " "Info: Detected ripple clock \"divider\[0\]\" as buffer" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } } { "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clk register low\[2\] register origin\[1\] 153.19 MHz 6.528 ns Internal " "Info: Clock \"sys_clk\" has Internal fmax of 153.19 MHz between source register \"low\[2\]\" and destination register \"origin\[1\]\" (period= 6.528 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.246 ns + Longest register register " "Info: + Longest register to register delay is 6.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns low\[2\] 1 REG LC_X13_Y12_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y12_N2; Fanout = 8; REG Node = 'low\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { low[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.225 ns) + CELL(0.442 ns) 2.667 ns Equal9~65 2 COMB LC_X15_Y5_N5 5 " "Info: 2: + IC(2.225 ns) + CELL(0.442 ns) = 2.667 ns; Loc. = LC_X15_Y5_N5; Fanout = 5; COMB Node = 'Equal9~65'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.667 ns" { low[2] Equal9~65 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.292 ns) 3.883 ns WideNor0~62 3 COMB LC_X14_Y5_N8 3 " "Info: 3: + IC(0.924 ns) + CELL(0.292 ns) = 3.883 ns; Loc. = LC_X14_Y5_N8; Fanout = 3; COMB Node = 'WideNor0~62'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.216 ns" { Equal9~65 WideNor0~62 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.442 ns) 5.516 ns WideNor0 4 COMB LC_X15_Y4_N1 1 " "Info: 4: + IC(1.191 ns) + CELL(0.442 ns) = 5.516 ns; Loc. = LC_X15_Y4_N1; Fanout = 1; COMB Node = 'WideNor0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { WideNor0~62 WideNor0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.309 ns) 6.246 ns origin\[1\] 5 REG LC_X15_Y4_N0 1 " "Info: 5: + IC(0.421 ns) + CELL(0.309 ns) = 6.246 ns; Loc. = LC_X15_Y4_N0; Fanout = 1; REG Node = 'origin\[1\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { WideNor0 origin[1] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.485 ns ( 23.78 % ) " "Info: Total cell delay = 1.485 ns ( 23.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.761 ns ( 76.22 % ) " "Info: Total interconnect delay = 4.761 ns ( 76.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.246 ns" { low[2] Equal9~65 WideNor0~62 WideNor0 origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "6.246 ns" { low[2] {} Equal9~65 {} WideNor0~62 {} WideNor0 {} origin[1] {} } { 0.000ns 2.225ns 0.924ns 1.191ns 0.421ns } { 0.000ns 0.442ns 0.292ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.021 ns - Smallest " "Info: - Smallest clock skew is -0.021 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 7.348 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clk\" to destination register is 7.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 26 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt\[23\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 7.348 ns origin\[1\] 3 REG LC_X15_Y4_N0 1 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 7.348 ns; Loc. = LC_X15_Y4_N0; Fanout = 1; REG Node = 'origin\[1\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.199 ns" { clk_cnt[23] origin[1] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.39 % ) " "Info: Total cell delay = 3.115 ns ( 42.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 57.61 % ) " "Info: Total interconnect delay = 4.233 ns ( 57.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 7.369 ns - Longest register " "Info: - Longest clock path from clock \"sys_clk\" to source register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 26 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt\[23\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns low\[2\] 3 REG LC_X13_Y12_N2 8 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X13_Y12_N2; Fanout = 8; REG Node = 'low\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.220 ns" { clk_cnt[23] low[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] low[2] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[2] {} } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] low[2] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[2] {} } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.246 ns" { low[2] Equal9~65 WideNor0~62 WideNor0 origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "6.246 ns" { low[2] {} Equal9~65 {} WideNor0~62 {} WideNor0 {} origin[1] {} } { 0.000ns 2.225ns 0.924ns 1.191ns 0.421ns } { 0.000ns 0.442ns 0.292ns 0.442ns 0.309ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.348 ns" { sys_clk clk_cnt[23] origin[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.348 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} origin[1] {} } { 0.000ns 0.000ns 0.745ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] low[2] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[23] {} low[2] {} } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "sys_clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"sys_clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sp~reg0 sp~reg0 sys_clk 259 ps " "Info: Found hold time violation between source  pin or register \"sp~reg0\" and destination pin or register \"sp~reg0\" for clock \"sys_clk\" (Hold time is 259 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.298 ns + Largest " "Info: + Largest clock skew is 1.298 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 12.380 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to destination register is 12.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.244 ns) + CELL(0.935 ns) 8.328 ns divider\[6\] 3 REG LC_X15_Y4_N9 3 " "Info: 3: + IC(4.244 ns) + CELL(0.935 ns) = 8.328 ns; Loc. = LC_X15_Y4_N9; Fanout = 3; REG Node = 'divider\[6\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { clk_cnt[2] divider[6] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.590 ns) 10.195 ns Equal0~164 4 COMB LC_X16_Y3_N7 1 " "Info: 4: + IC(1.277 ns) + CELL(0.590 ns) = 10.195 ns; Loc. = LC_X16_Y3_N7; Fanout = 1; COMB Node = 'Equal0~164'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.867 ns" { divider[6] Equal0~164 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 11.213 ns Equal0 5 COMB LC_X16_Y3_N4 15 " "Info: 5: + IC(0.428 ns) + CELL(0.590 ns) = 11.213 ns; Loc. = LC_X16_Y3_N4; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { Equal0~164 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.711 ns) 12.380 ns sp~reg0 6 REG LC_X16_Y3_N5 2 " "Info: 6: + IC(0.456 ns) + CELL(0.711 ns) = 12.380 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.230 ns ( 42.25 % ) " "Info: Total cell delay = 5.230 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.150 ns ( 57.75 % ) " "Info: Total interconnect delay = 7.150 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 11.082 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clk\" to source register is 11.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.244 ns) + CELL(0.935 ns) 8.328 ns divider\[8\] 3 REG LC_X15_Y3_N1 4 " "Info: 3: + IC(4.244 ns) + CELL(0.935 ns) = 8.328 ns; Loc. = LC_X15_Y3_N1; Fanout = 4; REG Node = 'divider\[8\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { clk_cnt[2] divider[8] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.114 ns) 9.180 ns Equal0~165 4 COMB LC_X16_Y3_N2 1 " "Info: 4: + IC(0.738 ns) + CELL(0.114 ns) = 9.180 ns; Loc. = LC_X16_Y3_N2; Fanout = 1; COMB Node = 'Equal0~165'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.852 ns" { divider[8] Equal0~165 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 9.915 ns Equal0 5 COMB LC_X16_Y3_N4 15 " "Info: 5: + IC(0.443 ns) + CELL(0.292 ns) = 9.915 ns; Loc. = LC_X16_Y3_N4; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Equal0~165 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.711 ns) 11.082 ns sp~reg0 6 REG LC_X16_Y3_N5 2 " "Info: 6: + IC(0.456 ns) + CELL(0.711 ns) = 11.082 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.456 ns ( 40.21 % ) " "Info: Total cell delay = 4.456 ns ( 40.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.626 ns ( 59.79 % ) " "Info: Total interconnect delay = 6.626 ns ( 59.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "11.082 ns" { sys_clk clk_cnt[2] divider[8] Equal0~165 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "11.082 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[8] {} Equal0~165 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 0.738ns 0.443ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } } { "e:/