ibelieve.map.qmsg

<I believe> song _verilog code for any device.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 16 11:00:41 2008 " "Info: Processing started: Wed Jul 16 11:00:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Ibelieve -c Ibelieve " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Ibelieve -c Ibelieve" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Ibelieve.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Ibelieve.v" { { "Info" "ISGN_ENTITY_NAME" "1 Ibelieve " "Info: Found entity 1: Ibelieve" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Ibelieve " "Info: Elaborating entity \"Ibelieve\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[3\] data_in GND " "Warning (14130): Reduced register \"high\[3\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[2\] data_in GND " "Warning (14130): Reduced register \"high\[2\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[1\] data_in GND " "Warning (14130): Reduced register \"high\[1\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[0\] data_in GND " "Warning (14130): Reduced register \"high\[0\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "med\[3\] data_in GND " "Warning (14130): Reduced register \"med\[3\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "low\[3\] data_in GND " "Warning (14130): Reduced register \"low\[3\]\" with stuck data_in port to stuck value GND" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "low\[1\] low\[2\] " "Info: Duplicate register \"low\[1\]\" merged to single register \"low\[2\]\"" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 53 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "origin\[5\] origin\[9\] " "Info: Duplicate register \"origin\[5\]\" merged to single register \"origin\[9\]\"" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "origin\[0\] origin\[4\] " "Info: Duplicate register \"origin\[0\]\" merged to single register \"origin\[4\]\"" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "118 " "Info: Implemented 118 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "115 " "Info: Implemented 115 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 16 11:00:43 2008 " "Info: Processing ended: Wed Jul 16 11:00:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}