prev_cmp_ibelieve.tan.qmsg

来自「<I believe> song _verilog code for」· QMSG 代码 · 共 11 行 · 第 1/4 页

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "sys_clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"sys_clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sp~reg0 sp~reg0 sys_clk 259 ps " "Info: Found hold time violation between source  pin or register \"sp~reg0\" and destination pin or register \"sp~reg0\" for clock \"sys_clk\" (Hold time is 259 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.298 ns + Largest " "Info: + Largest clock skew is 1.298 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 12.380 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to destination register is 12.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.244 ns) + CELL(0.935 ns) 8.328 ns divider\[6\] 3 REG LC_X15_Y4_N9 3 " "Info: 3: + IC(4.244 ns) + CELL(0.935 ns) = 8.328 ns; Loc. = LC_X15_Y4_N9; Fanout = 3; REG Node = 'divider\[6\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { clk_cnt[2] divider[6] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.590 ns) 10.195 ns Equal0~164 4 COMB LC_X16_Y3_N7 1 " "Info: 4: + IC(1.277 ns) + CELL(0.590 ns) = 10.195 ns; Loc. = LC_X16_Y3_N7; Fanout = 1; COMB Node = 'Equal0~164'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.867 ns" { divider[6] Equal0~164 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 11.213 ns Equal0 5 COMB LC_X16_Y3_N4 15 " "Info: 5: + IC(0.428 ns) + CELL(0.590 ns) = 11.213 ns; Loc. = LC_X16_Y3_N4; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { Equal0~164 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.711 ns) 12.380 ns sp~reg0 6 REG LC_X16_Y3_N5 2 " "Info: 6: + IC(0.456 ns) + CELL(0.711 ns) = 12.380 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.230 ns ( 42.25 % ) " "Info: Total cell delay = 5.230 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.150 ns ( 57.75 % ) " "Info: Total interconnect delay = 7.150 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 11.082 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clk\" to source register is 11.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.244 ns) + CELL(0.935 ns) 8.328 ns divider\[8\] 3 REG LC_X15_Y3_N1 4 " "Info: 3: + IC(4.244 ns) + CELL(0.935 ns) = 8.328 ns; Loc. = LC_X15_Y3_N1; Fanout = 4; REG Node = 'divider\[8\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { clk_cnt[2] divider[8] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.114 ns) 9.180 ns Equal0~165 4 COMB LC_X16_Y3_N2 1 " "Info: 4: + IC(0.738 ns) + CELL(0.114 ns) = 9.180 ns; Loc. = LC_X16_Y3_N2; Fanout = 1; COMB Node = 'Equal0~165'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.852 ns" { divider[8] Equal0~165 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 9.915 ns Equal0 5 COMB LC_X16_Y3_N4 15 " "Info: 5: + IC(0.443 ns) + CELL(0.292 ns) = 9.915 ns; Loc. = LC_X16_Y3_N4; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Equal0~165 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.711 ns) 11.082 ns sp~reg0 6 REG LC_X16_Y3_N5 2 " "Info: 6: + IC(0.456 ns) + CELL(0.711 ns) = 11.082 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.456 ns ( 40.21 % ) " "Info: Total cell delay = 4.456 ns ( 40.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.626 ns ( 59.79 % ) " "Info: Total interconnect delay = 6.626 ns ( 59.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "11.082 ns" { sys_clk clk_cnt[2] divider[8] Equal0~165 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "11.082 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[8] {} Equal0~165 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 0.738ns 0.443ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "11.082 ns" { sys_clk clk_cnt[2] divider[8] Equal0~165 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "11.082 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[8] {} Equal0~165 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 0.738ns 0.443ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.830 ns - Shortest register register " "Info: - Shortest register to register delay is 0.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sp~reg0 1 REG LC_X16_Y3_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.521 ns) + CELL(0.309 ns) 0.830 ns sp~reg0 2 REG LC_X16_Y3_N5 2 " "Info: 2: + IC(0.521 ns) + CELL(0.309 ns) = 0.830 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.23 % ) " "Info: Total cell delay = 0.309 ns ( 37.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.521 ns ( 62.77 % ) " "Info: Total interconnect delay = 0.521 ns ( 62.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { sp~reg0 {} sp~reg0 {} } { 0.000ns 0.521ns } { 0.000ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "11.082 ns" { sys_clk clk_cnt[2] divider[8] Equal0~165 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "11.082 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[8] {} Equal0~165 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 0.738ns 0.443ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "0.830 ns" { sp~reg0 {} sp~reg0 {} } { 0.000ns 0.521ns } { 0.000ns 0.309ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clk sp sp~reg0 17.163 ns register " "Info: tco from clock \"sys_clk\" to destination pin \"sp\" through register \"sp~reg0\" is 17.163 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 12.380 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to source register is 12.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_29 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.244 ns) + CELL(0.935 ns) 8.328 ns divider\[6\] 3 REG LC_X15_Y4_N9 3 " "Info: 3: + IC(4.244 ns) + CELL(0.935 ns) = 8.328 ns; Loc. = LC_X15_Y4_N9; Fanout = 3; REG Node = 'divider\[6\]'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { clk_cnt[2] divider[6] } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.590 ns) 10.195 ns Equal0~164 4 COMB LC_X16_Y3_N7 1 " "Info: 4: + IC(1.277 ns) + CELL(0.590 ns) = 10.195 ns; Loc. = LC_X16_Y3_N7; Fanout = 1; COMB Node = 'Equal0~164'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.867 ns" { divider[6] Equal0~164 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 11.213 ns Equal0 5 COMB LC_X16_Y3_N4 15 " "Info: 5: + IC(0.428 ns) + CELL(0.590 ns) = 11.213 ns; Loc. = LC_X16_Y3_N4; Fanout = 15; COMB Node = 'Equal0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { Equal0~164 Equal0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.711 ns) 12.380 ns sp~reg0 6 REG LC_X16_Y3_N5 2 " "Info: 6: + IC(0.456 ns) + CELL(0.711 ns) = 12.380 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { Equal0 sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.230 ns ( 42.25 % ) " "Info: Total cell delay = 5.230 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.150 ns ( 57.75 % ) " "Info: Total interconnect delay = 7.150 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.559 ns + Longest register pin " "Info: + Longest register to pin delay is 4.559 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sp~reg0 1 REG LC_X16_Y3_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y3_N5; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sp~reg0 } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 29 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.435 ns) + CELL(2.124 ns) 4.559 ns sp 2 PIN PIN_54 0 " "Info: 2: + IC(2.435 ns) + CELL(2.124 ns) = 4.559 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'sp'" {  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.559 ns" { sp~reg0 sp } "NODE_NAME" } } { "Ibelieve.v" "" { Text "D:/电子/FPGA学习/华清练习/I believe/Ibelieve.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 46.59 % ) " "Info: Total cell delay = 2.124 ns ( 46.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.435 ns ( 53.41 % ) " "Info: Total interconnect delay = 2.435 ns ( 53.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.559 ns" { sp~reg0 sp } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "4.559 ns" { sp~reg0 {} sp {} } { 0.000ns 2.435ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "12.380 ns" { sys_clk clk_cnt[2] divider[6] Equal0~164 Equal0 sp~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "12.380 ns" { sys_clk {} sys_clk~out0 {} clk_cnt[2] {} divider[6] {} Equal0~164 {} Equal0 {} sp~reg0 {} } { 0.000ns 0.000ns 0.745ns 4.244ns 1.277ns 0.428ns 0.456ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.559 ns" { sp~reg0 sp } "NODE_NAME" } } { "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/bin/Technology_Viewer.qrui" "4.559 ns" { sp~reg0 {} sp {} } { 0.000ns 2.435ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}