ibelieve.tan.summary

来自「<I believe> song _verilog code for」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.557 ns
From           : sp~reg0
To             : sp
From Clock     : sys_clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'sys_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 171.61 MHz ( period = 5.827 ns )
From           : low[0]
To             : origin[1]
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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