ibelieve.tan.rpt

<I believe> song _verilog code for any device.

    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Jul 16 11:00:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Ibelieve -c Ibelieve --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sys_clk" is an undefined clock
Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "divider[13]" as buffer
    Info: Detected ripple clock "divider[12]" as buffer
    Info: Detected ripple clock "divider[11]" as buffer
    Info: Detected ripple clock "divider[10]" as buffer
    Info: Detected ripple clock "divider[9]" as buffer
    Info: Detected ripple clock "divider[8]" as buffer
    Info: Detected ripple clock "divider[7]" as buffer
    Info: Detected ripple clock "divider[6]" as buffer
    Info: Detected ripple clock "divider[5]" as buffer
    Info: Detected ripple clock "clk_cnt[23]" as buffer
    Info: Detected ripple clock "divider[4]" as buffer
    Info: Detected ripple clock "divider[3]" as buffer
    Info: Detected ripple clock "divider[2]" as buffer
    Info: Detected gated clock "Equal0~164" as buffer
    Info: Detected gated clock "Equal0~163" as buffer
    Info: Detected gated clock "Equal0~165" as buffer
    Info: Detected gated clock "Equal0~166" as buffer
    Info: Detected ripple clock "divider[1]" as buffer
    Info: Detected ripple clock "clk_cnt[2]" as buffer
    Info: Detected ripple clock "divider[0]" as buffer
Info: Clock "sys_clk" has Internal fmax of 171.61 MHz between source register "low[0]" and destination register "origin[1]" (period= 5.827 ns)
    Info: + Longest register to register delay is 5.587 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N3; Fanout = 9; REG Node = 'low[0]'
        Info: 2: + IC(1.348 ns) + CELL(0.442 ns) = 1.790 ns; Loc. = LC_X20_Y14_N6; Fanout = 7; COMB Node = 'Equal5~81'
        Info: 3: + IC(0.809 ns) + CELL(0.590 ns) = 3.189 ns; Loc. = LC_X19_Y14_N7; Fanout = 3; COMB Node = 'WideNor0~62'
        Info: 4: + IC(1.226 ns) + CELL(0.442 ns) = 4.857 ns; Loc. = LC_X20_Y13_N1; Fanout = 1; COMB Node = 'WideNor0'
        Info: 5: + IC(0.421 ns) + CELL(0.309 ns) = 5.587 ns; Loc. = LC_X20_Y13_N0; Fanout = 1; REG Node = 'origin[1]'
        Info: Total cell delay = 1.783 ns ( 31.91 % )
        Info: Total interconnect delay = 3.804 ns ( 68.09 % )
    Info: - Smallest clock skew is 0.021 ns
        Info: + Shortest clock path from clock "sys_clk" to destination register is 7.408 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'
            Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt[23]'
            Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X20_Y13_N0; Fanout = 1; REG Node = 'origin[1]'
            Info: Total cell delay = 3.115 ns ( 42.05 % )
            Info: Total interconnect delay = 4.293 ns ( 57.95 % )
        Info: - Longest clock path from clock "sys_clk" to source register is 7.387 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'
            Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 26; REG Node = 'clk_cnt[23]'
            Info: 3: + IC(3.527 ns) + CELL(0.711 ns) = 7.387 ns; Loc. = LC_X20_Y10_N3; Fanout = 9; REG Node = 'low[0]'
            Info: Total cell delay = 3.115 ns ( 42.17 % )
            Info: Total interconnect delay = 4.272 ns ( 57.83 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "sys_clk" to destination pin "sp" through register "sp~reg0" is 18.557 ns
    Info: + Longest clock path from clock "sys_clk" to source register is 12.168 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'
        Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt[2]'
        Info: 3: + IC(4.304 ns) + CELL(0.935 ns) = 8.388 ns; Loc. = LC_X20_Y13_N6; Fanout = 4; REG Node = 'divider[3]'
        Info: 4: + IC(1.280 ns) + CELL(0.590 ns) = 10.258 ns; Loc. = LC_X21_Y12_N2; Fanout = 1; COMB Node = 'Equal0~163'
        Info: 5: + IC(0.450 ns) + CELL(0.292 ns) = 11.000 ns; Loc. = LC_X21_Y12_N6; Fanout = 15; COMB Node = 'Equal0'
        Info: 6: + IC(0.457 ns) + CELL(0.711 ns) = 12.168 ns; Loc. = LC_X21_Y12_N9; Fanout = 2; REG Node = 'sp~reg0'
        Info: Total cell delay = 4.932 ns ( 40.53 % )
        Info: Total interconnect delay = 7.236 ns ( 59.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.165 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y12_N9; Fanout = 2; REG Node = 'sp~reg0'
        Info: 2: + IC(4.057 ns) + CELL(2.108 ns) = 6.165 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sp'
        Info: Total cell delay = 2.108 ns ( 34.19 % )
        Info: Total interconnect delay = 4.057 ns ( 65.81 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Wed Jul 16 11:00:51 2008
    Info: Elapsed time: 00:00:00