list_presets.do

nios num clock verilog code

onerr {resume}
add list -bin /test_bench/clk
add list -hex /test_bench/DUT/the_onchip_ram_4K/az_addr
add list -hex /test_bench/DUT/the_onchip_ram_4K/az_be_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/az_cs
add list -hex /test_bench/DUT/the_onchip_ram_4K/az_data
add list -bin /test_bench/DUT/the_onchip_ram_4K/az_rd_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/az_wr_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/clk
add list -hex /test_bench/DUT/the_onchip_ram_4K/za_data
add list -bin /test_bench/DUT/the_onchip_ram_4K/za_valid
add list -bin /test_bench/DUT/the_onchip_ram_4K/za_waitrequest
add list -asc /test_bench/DUT/the_onchip_ram_4K/CODE
add list -hex /test_bench/DUT/the_onchip_ram_4K/zs_addr
add list -hex /test_bench/DUT/the_onchip_ram_4K/zs_ba
add list -hex /test_bench/DUT/the_onchip_ram_4K/zs_cs_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/zs_ras_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/zs_cas_n
add list -bin /test_bench/DUT/the_onchip_ram_4K/zs_we_n
add list -hex /test_bench/DUT/the_onchip_ram_4K/zs_dq
add list -hex /test_bench/DUT/the_onchip_ram_4K/zs_dqm
add list -hex /test_bench/DUT/the_sdram/az_addr
add list -hex /test_bench/DUT/the_sdram/az_be_n
add list -bin /test_bench/DUT/the_sdram/az_cs
add list -hex /test_bench/DUT/the_sdram/az_data
add list -bin /test_bench/DUT/the_sdram/az_rd_n
add list -bin /test_bench/DUT/the_sdram/az_wr_n
add list -bin /test_bench/DUT/the_sdram/clk
add list -hex /test_bench/DUT/the_sdram/za_data
add list -bin /test_bench/DUT/the_sdram/za_valid
add list -bin /test_bench/DUT/the_sdram/za_waitrequest
add list -asc /test_bench/DUT/the_sdram/CODE
add list -hex /test_bench/DUT/the_sdram/zs_addr
add list -hex /test_bench/DUT/the_sdram/zs_ba
add list -hex /test_bench/DUT/the_sdram/zs_cs_n
add list -bin /test_bench/DUT/the_sdram/zs_ras_n
add list -bin /test_bench/DUT/the_sdram/zs_cas_n
add list -bin /test_bench/DUT/the_sdram/zs_we_n
add list -hex /test_bench/DUT/the_sdram/zs_dq
add list -hex /test_bench/DUT/the_sdram/zs_dqm
add list -hex /test_bench/DUT/the_jtag_uart/av_address
add list -bin /test_bench/DUT/the_jtag_uart/av_chipselect
add list -bin /test_bench/DUT/the_jtag_uart/av_irq
add list -bin /test_bench/DUT/the_jtag_uart/av_read_n
add list -hex /test_bench/DUT/the_jtag_uart/av_readdata
add list -bin /test_bench/DUT/the_jtag_uart/av_waitrequest
add list -bin /test_bench/DUT/the_jtag_uart/av_write_n
add list -hex /test_bench/DUT/the_jtag_uart/av_writedata
add list -bin /test_bench/DUT/the_jtag_uart/dataavailable
add list -bin /test_bench/DUT/the_jtag_uart/readyfordata
add list -hex /test_bench/DUT/the_cpu/d_irq
add list -hex /test_bench/DUT/the_cpu/d_waitrequest
add list -hex /test_bench/DUT/the_cpu/d_address
add list -hex /test_bench/DUT/the_cpu/d_byteenable
add list -hex /test_bench/DUT/the_cpu/d_read
add list -hex /test_bench/DUT/the_cpu/d_readdata
add list -hex /test_bench/DUT/the_cpu/d_write
add list -hex /test_bench/DUT/the_cpu/d_writedata
add list -hex /test_bench/DUT/the_cpu/i_waitrequest
add list -hex /test_bench/DUT/the_cpu/i_address
add list -hex /test_bench/DUT/the_cpu/i_read
add list -hex /test_bench/DUT/the_cpu/i_readdata
add list -hex /test_bench/DUT/the_cpu/the_cpu_test_bench/F_pcb
add list -asc /test_bench/DUT/the_cpu/the_cpu_test_bench/W_vinst
add list -hex /test_bench/DUT/the_cpu/the_cpu_test_bench/W_valid
add list -hex /test_bench/DUT/the_cpu/the_cpu_test_bench/D_iw
add list -bin /test_bench/DUT/the_uart/chipselect
add list -hex /test_bench/DUT/the_uart/address
add list -hex /test_bench/DUT/the_uart/writedata
add list -hex /test_bench/DUT/the_uart/readdata
add list -bin /test_bench/DUT/the_uart/tx_ready
add list -asc /test_bench/DUT/the_uart/tx_data
add list -bin /test_bench/DUT/the_uart/rx_char_ready
add list -asc /test_bench/DUT/the_uart/rx_data
configure list -usestrobe 0
configure list -strobestart {0 ps} -strobeperiod {0 ps}
configure list -delta none
configure list -usegating 1
configure list -gateexpr { /test_bench/clk'rising }