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关于波形发生功能的Verilog代码和Quartus文件完整文档。

wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~197 ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[0] ;
wire \auto_signaltap_0|acq_trigger_in_reg[6] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|match_out ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[2] ;
wire \auto_signaltap_0|acq_trigger_in_reg[8] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|match_out ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[3] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|p_match_out~206 ;
wire \auto_signaltap_0|acq_trigger_in_reg[9] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|match_out ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[1] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|p_match_out~206 ;
wire \auto_signaltap_0|acq_trigger_in_reg[7] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~198 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|p_match_out~209 ;
wire \auto_signaltap_0|acq_trigger_in_reg[13] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~206 ;
wire \auto_signaltap_0|acq_trigger_in_reg[0] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|acq_trigger_in_reg[1] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~196 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~200 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened_ff[1] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[6] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[5] ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~171 ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|process0~19 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened_ff[0] ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~201 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~202 ;
wire \sld_hub_inst|IRSR|Q[7] ;
wire \sld_hub_inst|IRSR|Q[6] ;
wire \sld_hub_inst|IRSR|Q[5] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|process4~24 ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3] ;
wire \sld_hub_inst|IRSR|Q[4] ;
wire \sld_hub_inst|IRSR|Q[3]~386 ;
wire \sld_hub_inst|IRSR|Q[3]~387 ;
wire \sld_hub_inst|IRSR|Q[3]~388 ;
wire \sld_hub_inst|IRSR|Q[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[1] ;
wire \sld_hub_inst|BROADCAST|Q[0] ;
wire \sld_hub_inst|comb~7 ;
wire \sld_hub_inst|RESET|Q[0] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:2:S_IRF|Q[0] ;
wire \sld_hub_inst|\GEN_IRF:2:IRF|Q[0] ;
wire \auto_signaltap_0|reset_all ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella10 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|stop_acquisition~100 ;
wire \auto_signaltap_0|ela_control|sm1|ela_done ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[3] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[4] ;
wire \auto_signaltap_0|ela_control|sm1|edq~69 ;
wire \auto_signaltap_0|ela_control|sm1|buffer_write_enable ;
wire \auto_signaltap_0|ela_control|ela_status~131 ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0] ;
wire \sld_hub_inst|IRSR|Q[1] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[7] ;
wire \sld_hub_inst|CLEAR_SIGNAL~0 ;
wire \sld_hub_inst|IRSR|Q[8] ;
wire \sld_hub_inst|IRF_ENA|Q[1] ;
wire \auto_signaltap_0|sdr~13 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|trigger_write_addr_latch_ena ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[8] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[9] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[10] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[11] ;
wire \~GND ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:2:S_IRF|Q[4] ;
wire \sld_hub_inst|\GEN_IRF:2:IRF|Q[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella0~COUTCOUT1_17 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella1~COUTCOUT1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_16 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella3~COUTCOUT1_16 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|modulus_trigger ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|reduce_nor~1 ;
wire \auto_signaltap_0|ela_control|buffer_write_ena_int~42 ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][5] ;
wire \auto_signaltap_0|comb~28 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~29 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|reduce_nor~0 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella1~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella3~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella4~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella6~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[7] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella7~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella8~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella9~COUTCOUT1_1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella10~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[11] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[5] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][13] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[13] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[13] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][12] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[12] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[12] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][11] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[11] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[11] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][10] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[10] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[10] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][9] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[9] ;