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关于波形发生功能的Verilog代码和Quartus文件完整文档。

wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[1] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[0] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[20] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[19] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[18] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[17] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[16] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[15] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[14] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[13] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[12] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[11] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[8] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~84 ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[7] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~79 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~80 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~78 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~81 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~82 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~83 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|is_buffer_wrapped~0 ;
wire \auto_signaltap_0|ela_control|buffer_write_addr_adv_ena_int~53 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella1~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella3~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella4~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[5] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella6~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[7] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella7~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella8~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella9~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella10~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[11] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella11~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella11~COUTCOUT1_1 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|cout ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|is_buffer_wrapped_once ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella4~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella9 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella9~COUTCOUT1_2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella10~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella11 ;
wire \auto_signaltap_0|ela_control|sm1|post_trigger_count_enable~107 ;
wire \auto_signaltap_0|ela_control|sm1|post_trigger_count_enable ;
wire \auto_signaltap_0|ela_control|sm2|status_out~110 ;
wire \auto_signaltap_0|ela_control|sm2|status_out[0] ;
wire \auto_signaltap_0|ela_control|ela_status~130 ;
wire \sld_hub_inst|IRSR|Q[0]~384 ;
wire \sld_hub_inst|IRSR_ENA ;
wire \sld_hub_inst|IRSR|Q[0]~385 ;
wire \sld_hub_inst|IRSR|Q[0] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[0] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|process0~12 ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|process1~1 ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[0] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[1]~47 ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7]~643 ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[0] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[1] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[1] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[2] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[2] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[3] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[3] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[4] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[4] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[5] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[6] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_b[7] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7] ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[4] ;
wire \auto_signaltap_0|acq_trigger_in_reg[10] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|match_out ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[5] ;
wire \auto_signaltap_0|acq_trigger_in_reg[11] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|match_out ;
wire \inst1|altsyncram_component|auto_generated|altsyncram1|q_a[6] ;
wire \auto_signaltap_0|acq_trigger_in_reg[12] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~199 ;
wire \auto_signaltap_0|acq_trigger_in_reg[2] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|match_out ;
wire \auto_signaltap_0|acq_trigger_in_reg[3] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|p_match_out~206 ;
wire \auto_signaltap_0|acq_trigger_in_reg[4] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|p_match_out~173 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|match_out ;