wave.vo

关于波形发生功能的Verilog代码和Quartus文件完整文档。

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "06/06/2006 22:38:24"

// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 10 ps/ 1 ps

module 	WAVE (
	mclk,
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	\output ,
	address,
	q,
	altera_reserved_tdo);
input 	mclk;
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
output 	\output ;
output 	[5:0] address;
output 	[7:0] q;
output 	altera_reserved_tdo;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("WAVE_v.sdo");
// synopsys translate_on

wire \auto_signaltap_0|bypass_reg_out ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[0] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|bypass_reg_out ;
wire \auto_signaltap_0|ela_control|sm2|status_out[2] ;
wire \inst1|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[2] ;
wire \auto_signaltap_0|ela_control|sm2|status_out[1] ;
wire \mclk~combout ;
wire \inst2|add~251 ;
wire \inst2|count[12]~1110 ;
wire \inst2|count[0] ;
wire \inst2|add~253 ;
wire \inst2|add~256 ;
wire \inst2|count[1] ;
wire \inst2|add~258 ;
wire \inst2|add~258COUT1_262 ;
wire \inst2|add~211 ;
wire \inst2|count[2] ;
wire \inst2|add~213 ;
wire \inst2|add~213COUT1_263 ;
wire \inst2|add~216 ;
wire \inst2|count[3] ;
wire \inst2|add~218 ;
wire \inst2|add~218COUT1_264 ;
wire \inst2|add~226 ;
wire \inst2|count[4] ;
wire \inst2|add~228 ;
wire \inst2|add~228COUT1_265 ;
wire \inst2|add~221 ;
wire \inst2|count[5] ;
wire \inst2|add~223 ;
wire \inst2|add~246 ;
wire \inst2|count[6] ;
wire \inst2|reduce_nor~63 ;
wire \inst2|add~248 ;
wire \inst2|add~248COUT1_266 ;
wire \inst2|add~241 ;
wire \inst2|count[7] ;
wire \inst2|add~243 ;
wire \inst2|add~243COUT1_267 ;
wire \inst2|add~236 ;
wire \inst2|count[8] ;
wire \inst2|add~238 ;
wire \inst2|add~238COUT1_268 ;
wire \inst2|add~231 ;
wire \inst2|count[9] ;
wire \inst2|reduce_nor~61 ;
wire \inst2|reduce_nor~62 ;
wire \inst2|count[12]~1103 ;
wire \inst2|add~233 ;
wire \inst2|add~233COUT1_269 ;
wire \inst2|add~198 ;
wire \inst2|add~203 ;
wire \inst2|add~203COUT1_270 ;
wire \inst2|add~206 ;
wire \inst2|count[12]~1107 ;
wire \inst2|count[12] ;
wire \inst2|count[10]~1104 ;
wire \inst2|add~196 ;
wire \inst2|count[10] ;
wire \inst2|LessThan~410 ;
wire \inst2|reduce_nor~60 ;
wire \inst2|LessThan~411 ;
wire \inst2|add~201 ;
wire \inst2|count[11] ;
wire \inst2|clk~248 ;
wire \inst2|clk~244 ;
wire \inst2|clk~245 ;
wire \inst2|clk~246 ;
wire \inst2|clk~247 ;
wire \inst2|clk ;
wire \inst|lpm_counter_component|auto_generated|safe_q[0] ;
wire \inst|lpm_counter_component|auto_generated|counter_cella0~COUT ;
wire \inst|lpm_counter_component|auto_generated|counter_cella0~COUTCOUT1_1 ;
wire \inst|lpm_counter_component|auto_generated|safe_q[1] ;
wire \inst|lpm_counter_component|auto_generated|counter_cella1~COUT ;
wire \inst|lpm_counter_component|auto_generated|counter_cella1~COUTCOUT1_1 ;
wire \inst|lpm_counter_component|auto_generated|safe_q[2] ;
wire \inst|lpm_counter_component|auto_generated|counter_cella2~COUT ;
wire \inst|lpm_counter_component|auto_generated|counter_cella2~COUTCOUT1 ;
wire \inst|lpm_counter_component|auto_generated|safe_q[3] ;
wire \inst|lpm_counter_component|auto_generated|counter_cella3~COUT ;
wire \inst|lpm_counter_component|auto_generated|safe_q[4] ;
wire \inst|lpm_counter_component|auto_generated|counter_cella4~COUT ;
wire \inst|lpm_counter_component|auto_generated|counter_cella4~COUTCOUT1_1 ;
wire \inst|lpm_counter_component|auto_generated|safe_q[5] ;
wire \altera_reserved_tck~combout ;
wire \altera_reserved_tdi~combout ;
wire \altera_internal_jtag~TMSUTAP ;
wire \sld_hub_inst|jtag_state_machine|state[10] ;
wire \sld_hub_inst|jtag_state_machine|state[13] ;
wire \sld_hub_inst|jtag_state_machine|state[14] ;
wire \sld_hub_inst|jtag_state_machine|state[11] ;
wire \sld_hub_inst|jtag_state_machine|state[12] ;
wire \sld_hub_inst|jtag_state_machine|state[15] ;
wire \sld_hub_inst|jtag_state_machine|state[3] ;