📄 cont.tan.rpt
字号:
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; cnt0[3] ; cnt1[2] ; clk ; clk ; None ; None ; 5.800 ns ;
; N/A ; 147.06 MHz ( period = 6.800 ns ) ; cnt1[0] ; co~reg0 ; clk ; clk ; None ; None ; 5.700 ns ;
; N/A ; 149.25 MHz ( period = 6.700 ns ) ; cnt0[2] ; cnt1[0] ; clk ; clk ; None ; None ; 5.600 ns ;
; N/A ; 151.52 MHz ( period = 6.600 ns ) ; cnt0[1] ; cnt1[0] ; clk ; clk ; None ; None ; 5.500 ns ;
; N/A ; 151.52 MHz ( period = 6.600 ns ) ; cnt0[0] ; cnt1[0] ; clk ; clk ; None ; None ; 5.500 ns ;
; N/A ; 153.85 MHz ( period = 6.500 ns ) ; cnt0[2] ; co~reg0 ; clk ; clk ; None ; None ; 5.400 ns ;
; N/A ; 156.25 MHz ( period = 6.400 ns ) ; cnt0[1] ; co~reg0 ; clk ; clk ; None ; None ; 5.300 ns ;
; N/A ; 156.25 MHz ( period = 6.400 ns ) ; cnt0[0] ; co~reg0 ; clk ; clk ; None ; None ; 5.300 ns ;
; N/A ; 163.93 MHz ( period = 6.100 ns ) ; cnt1[1] ; cnt1[1] ; clk ; clk ; None ; None ; 5.000 ns ;
; N/A ; 163.93 MHz ( period = 6.100 ns ) ; cnt1[1] ; cnt1[2] ; clk ; clk ; None ; None ; 5.000 ns ;
; N/A ; 166.67 MHz ( period = 6.000 ns ) ; cnt1[2] ; cnt1[1] ; clk ; clk ; None ; None ; 4.900 ns ;
; N/A ; 166.67 MHz ( period = 6.000 ns ) ; cnt1[2] ; cnt1[2] ; clk ; clk ; None ; None ; 4.900 ns ;
; N/A ; 178.57 MHz ( period = 5.600 ns ) ; cnt0[3] ; cnt0[2] ; clk ; clk ; None ; None ; 4.500 ns ;
; N/A ; 178.57 MHz ( period = 5.600 ns ) ; cnt0[3] ; cnt0[1] ; clk ; clk ; None ; None ; 4.500 ns ;
; N/A ; 196.08 MHz ( period = 5.100 ns ) ; cnt1[1] ; cnt0[2] ; clk ; clk ; None ; None ; 4.000 ns ;
; N/A ; 196.08 MHz ( period = 5.100 ns ) ; cnt1[1] ; cnt0[1] ; clk ; clk ; None ; None ; 4.000 ns ;
; N/A ; 200.00 MHz ( period = 5.000 ns ) ; cnt0[3] ; cnt1[0] ; clk ; clk ; None ; None ; 3.900 ns ;
; N/A ; 200.00 MHz ( period = 5.000 ns ) ; cnt1[2] ; cnt0[2] ; clk ; clk ; None ; None ; 3.900 ns ;
; N/A ; 200.00 MHz ( period = 5.000 ns ) ; cnt1[2] ; cnt0[1] ; clk ; clk ; None ; None ; 3.900 ns ;
; N/A ; 200.00 MHz ( period = 5.000 ns ) ; cnt0[3] ; co~reg0 ; clk ; clk ; None ; None ; 3.900 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[3] ; cnt0[3] ; clk ; clk ; None ; None ; 3.400 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt1[1] ; cnt1[0] ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt1[2] ; cnt1[0] ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[2] ; cnt0[3] ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[1] ; cnt0[3] ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt1[1] ; co~reg0 ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt1[2] ; co~reg0 ; clk ; clk ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[0] ; cnt0[3] ; clk ; clk ; None ; None ; 3.100 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[2] ; cnt0[0] ; clk ; clk ; None ; None ; 1.400 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[3] ; cnt0[0] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[1] ; cnt0[0] ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; co~reg0 ; co~reg0 ; clk ; clk ; None ; None ; 1.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; cnt0[0] ; cnt0[0] ; clk ; clk ; None ; None ; 1.100 ns ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+-------+------------+
; N/A ; None ; 11.500 ns ; cnt0[3] ; s0[3] ; clk ;
; N/A ; None ; 11.500 ns ; cnt1[0] ; s1[0] ; clk ;
; N/A ; None ; 11.300 ns ; cnt0[1] ; s0[1] ; clk ;
; N/A ; None ; 11.300 ns ; cnt1[1] ; s1[1] ; clk ;
; N/A ; None ; 10.400 ns ; co~reg0 ; co ; clk ;
; N/A ; None ; 10.400 ns ; cnt0[2] ; s0[2] ; clk ;
; N/A ; None ; 10.400 ns ; cnt1[2] ; s1[2] ; clk ;
; N/A ; None ; 9.900 ns ; cnt0[0] ; s0[0] ; clk ;
+-------+--------------+------------+---------+-------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Mon Dec 01 12:43:39 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cont -c cont
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 114.94 MHz between source register "cnt1[0]" and destination register "cnt1[1]" (period= 8.7 ns)
Info: + Longest register to register delay is 7.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A2; Fanout = 6; REG Node = 'cnt1[0]'
Info: 2: + IC(0.900 ns) + CELL(1.400 ns) = 2.300 ns; Loc. = LC1_A1; Fanout = 1; COMB Node = 'process0~60'
Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.600 ns; Loc. = LC2_A2; Fanout = 5; COMB Node = 'process0~0'
Info: 4: + IC(0.300 ns) + CELL(1.400 ns) = 6.300 ns; Loc. = LC7_A2; Fanout = 2; COMB Node = 'cnt1[0]~464'
Info: 5: + IC(0.300 ns) + CELL(1.000 ns) = 7.600 ns; Loc. = LC4_A2; Fanout = 5; REG Node = 'cnt1[1]'
Info: Total cell delay = 5.200 ns ( 68.42 % )
Info: Total interconnect delay = 2.400 ns ( 31.58 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_A2; Fanout = 5; REG Node = 'cnt1[1]'
Info: Total cell delay = 2.000 ns ( 83.33 % )
Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: - Longest clock path from clock "clk" to source register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_A2; Fanout = 6; REG Node = 'cnt1[0]'
Info: Total cell delay = 2.000 ns ( 83.33 % )
Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: + Micro clock to output delay of source is 0.500 ns
Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "s0[3]" through register "cnt0[3]" is 11.500 ns
Info: + Longest clock path from clock "clk" to source register is 2.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_A1; Fanout = 5; REG Node = 'cnt0[3]'
Info: Total cell delay = 2.000 ns ( 83.33 % )
Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: + Micro clock to output delay of source is 0.500 ns
Info: + Longest register to pin delay is 8.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A1; Fanout = 5; REG Node = 'cnt0[3]'
Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 's0[3]'
Info: Total cell delay = 6.300 ns ( 73.26 % )
Info: Total interconnect delay = 2.300 ns ( 26.74 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 107 megabytes of memory during processing
Info: Processing ended: Mon Dec 01 12:43:40 2008
Info: Elapsed time: 00:00:01
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