sha1_reg.vhd

本算法基于leon2协处理器接口标准

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY sha1_reg IS
    PORT(
        LOAD_I   :      IN      std_logic;
        
        DATA_I   :      IN      std_logic_vector(255 DOWNTO 0);
        WT       :      IN      std_logic_vector(31 DOWNTO 0);
        
        LSHH     :      IN      std_logic;
        LSHL     :      IN      std_logic;
        WS       :      IN      std_logic;                            -- write serial
        SEL      :      IN      std_logic_vector(3 DOWNTO 0);
        
        CLK      :      IN      std_logic;
        RST      :      IN      std_logic;
        
        DATA_O   :      OUT     std_logic_vector(127 DOWNTO 0)
        );
END sha1_reg;

ARCHITECTURE behavioral OF sha1_reg IS

   SIGNAL W0                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W1                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W2                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W3                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W4                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W5                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W6                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W7                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W8                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W9                       :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W10                      :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W11                      :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W12                      :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W13                      :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W14                      :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL W15                      :  std_logic_vector(31 DOWNTO 0);   
   
   BEGIN
       PROCESS(CLK)
          BEGIN
             IF (Clk'event AND CLK = '1') THEN
               IF (RST = '0') THEN          -- reset '0' is active
                 W0  <= X"00000000";     
                 W1  <= X"00000000";    
                 W2  <= X"00000000";    
                 W3  <= X"00000000";    
                 W4  <= X"00000000";    
                 W5  <= X"00000000";    
                 W6  <= X"00000000";    
                 W7  <= X"00000000";    
                 W8  <= X"00000000";    
                 W9  <= X"00000000";    
                 W10 <= X"00000000";    
                 W11 <= X"00000000";    
                 W12 <= X"00000000";    
                 W13 <= X"00000000";    
                 W14 <= X"00000000";
                 W15 <= X"00000000";
               END IF;
               
               IF (LSHL = '1' AND LOAD_I = '1') THEN         -- load the low 256 bits into registers w0~w7
                 W0  <= DATA_I(31  DOWNTO 0);    
                 W1  <= DATA_I(63  DOWNTO 32);    
                 W2  <= DATA_I(95  DOWNTO 64);    
                 W3  <= DATA_I(127 DOWNTO 96);    
                 W4  <= DATA_I(159 DOWNTO 128);    
                 W5  <= DATA_I(191 DOWNTO 160);    
                 W6  <= DATA_I(223 DOWNTO 192);    
                 W7  <= DATA_I(255 DOWNTO 224);
               END IF;
               
               IF (LSHH = '1' AND LOAD_I = '1') THEN          -- load the high 256 bits into registers w8~w15
                 W8  <= DATA_I(31  DOWNTO 0);    
                 W9  <= DATA_I(63  DOWNTO 32);    
                 W10 <= DATA_I(95  DOWNTO 64);    
                 W11 <= DATA_I(127 DOWNTO 96);    
                 W12 <= DATA_I(159 DOWNTO 128);    
                 W13 <= DATA_I(191 DOWNTO 160);    
                 W14 <= DATA_I(223 DOWNTO 192);    
                 W15 <= DATA_I(255 DOWNTO 224);
               END IF; 
               
              IF(WS = '1') THEN              -- shift w0~w15
                 W0 <= W1;    
                 W1 <= W2;    
                 W2 <= W3;    
                 W3 <= W4;    
                 W4 <= W5;    
                 W5 <= W6;    
                 W6 <= W7;    
                 W7 <= W8;    
                 W8 <= W9;    
                 W9 <= W10;    
                 W10 <= W11;    
                 W11 <= W12;    
                 W12 <= W13;    
                 W13 <= W14;    
                 W14 <= W15;    
                 W15 <= WT;
              END IF;
            END IF;
        END PROCESS;

        
          
          PROCESS(SEL,W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14,W15)
            BEGIN
            CASE SEL IS                        -- select output data
               WHEN "0001" =>
                 DATA_O(31  DOWNTO 0)   <= W0;
                 DATA_O(63  DOWNTO 32)  <= W1;
                 DATA_O(95  DOWNTO 64)  <= W2;
                 DATA_O(127 DOWNTO 96)  <= W3;
               WHEN "0010" =>
                 DATA_O(31  DOWNTO 0)   <= W4;
                 DATA_O(63  DOWNTO 32)  <= W5;
                 DATA_O(95  DOWNTO 64)  <= W6;
                 DATA_O(127 DOWNTO 96)  <= W7;
               WHEN "0100" =>
                 DATA_O(31  DOWNTO 0)   <= W8;
                 DATA_O(63  DOWNTO 32)  <= W9;
                 DATA_O(95  DOWNTO 64)  <= W10;
                 DATA_O(127 DOWNTO 96)  <= W11;
               WHEN "1000" =>
                 DATA_O(31  DOWNTO 0)   <= W12;
                 DATA_O(63  DOWNTO 32)  <= W13;
                 DATA_O(95  DOWNTO 64)  <= W14;
                 DATA_O(127 DOWNTO 96)  <= W15;
               WHEN "1111" =>
                 DATA_O(31  DOWNTO 0)   <= W0;
                 DATA_O(63  DOWNTO 32)  <= W2;
                 DATA_O(95  DOWNTO 64)  <= W8;
                 DATA_O(127 DOWNTO 96)  <= W13;
               WHEN OTHERS =>
                 NULL;
            END CASE;
        END PROCESS;
   END  behavioral;