sha1_2fa_slice.vhd

来自「本算法基于leon2协处理器接口标准」· VHDL 代码 · 共 65 行

------------------------------------------------------------------------
--
-- sha1_2fa_slice used in the wallace-tree
--
------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_2fa_slice IS
    PORT (
          a       : IN  std_logic;
          b       : IN  std_logic;
          c       : IN  std_logic;
          d       : IN  std_logic;
          e       : IN  std_logic;
          f        : IN  std_logic;
          cout0   : OUT std_logic;
          cout1   : OUT std_logic;                   
          sum0    : OUT std_logic;
          sum1    : OUT std_logic
          );
END sha1_2fa_slice;


-- description of adder using concurrent signal assignments
ARCHITECTURE rtl OF sha1_2fa_slice IS
     
    COMPONENT sha1_fa
    PORT (
          a    : in std_logic;
          b    : in std_logic;
          cin  : in std_logic;
          sum  : out std_logic;
          cout : out std_logic
          );
    END COMPONENT;
     
    SIGNAL    sum0_internal    :  std_logic;
     
BEGIN

   sum1 <= f;
   
   ADDR1: sha1_fa
   PORT MAP(
      a    => a,
      b    => b,
      cin  => c,
      sum  => sum0_internal,
      cout => cout0
      );
      
   ADDR2: sha1_fa
   PORT MAP(
      a    => sum0_internal,
      b    => d,
      cin  => e,
      sum  => sum0,
      cout => cout1
      );

END rtl;