sha1_32add.vhd

来自「本算法基于leon2协处理器接口标准」· VHDL 代码 · 共 25 行

------------------------------------------------------------------------
--
-- Single-bit adder
--
------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY sha1_32add IS
    PORT (
          a      : in std_logic_vector(31 DOWNTO 0);
          b      : in std_logic_vector(31 DOWNTO 0);
          c      : out std_logic_vector(31 DOWNTO 0)
          );
END sha1_32add;


-- description of adder using concurrent signal assignments
ARCHITECTURE rtl OF sha1_32add IS
BEGIN
         c <= a+b;
END rtl;