with_sdram_daq.fit.summary

fpga开发pci的verilog

Flow Status : Flow Failed - Tue Nov 13 15:29:12 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : WITH_SDRAM_DAQ
Top-level Entity Name : WITH_SDRAM_DAQ
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 2,383 / 5,980 ( 39 % )
Total pins : 119 / 185 ( 64 % )
Total virtual pins : 0
Total memory bits : 128,512 / 92,160 ( 139 % )
Total PLLs : 1 / 2 ( 50 % )