_primary.vhd

来自「Full AES Simulation Code」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity tb_vlog is
    generic(
        SYS_CLK_CYCLE   : integer := 50;
        KEYREG_LO       : integer := 8;
        KEYREG_HI       : integer := 9;
        KCTRL_ADDR      : integer := 12;
        DCTRL_ADDR      : integer := 13
    );
end tb_vlog;